Bill Schmidt ae8a966ad7 This patch addresses an incorrect transformation in the DAG combiner. ... The included test case is derived from one of the GCC compatibility tests. The problem arises after the selection DAG has been converted to type-legalized form. The combiner first sees a 64-bit load that can be converted into a pre-increment form. The original load feeds into a SRL that isolates the upper 32 bits of the loaded doubleword. This looks like an opportunity for DAGCombiner::ReduceLoadWidth() to replace the 64-bit load with a 32-bit load. However, this transformation is not valid, as the replacement load is not a pre-increment load. The pre-increment load produces an extra result, which feeds a subsequent add instruction. The replacement load only has one result value, and this value is propagated to all uses of the pre- increment load, including the add. Because the add is looking for the second result value as its operand, it ends up attempting to add a constant to a token chain, resulting in a crash. So the patch simply disables this transformation for any load with more than two result values. llvm-svn: 172480		2013-01-14 22:04:38 +00:00
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ARM	Simplify writing floating types to assembly.	2013-01-11 10:36:13 +00:00
CPP
Generic	For inline asm:	2013-01-11 18:12:39 +00:00
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MBlaze
Mips	[mips] MipsTargetLowering::getSetCCResultType should return a vector type if	2013-01-04 20:06:01 +00:00
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PowerPC	This patch addresses an incorrect transformation in the DAG combiner.	2013-01-14 22:04:38 +00:00
R600	DAGCombiner: Avoid generating illegal vector INT_TO_FP nodes	2013-01-02 22:13:01 +00:00
SI
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XCore