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to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
88 lines
3.3 KiB
C++
88 lines
3.3 KiB
C++
//===---------------------- RetireControlUnit.cpp ---------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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///
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/// This file simulates the hardware responsible for retiring instructions.
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///
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//===----------------------------------------------------------------------===//
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#include "llvm/MCA/HardwareUnits/RetireControlUnit.h"
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#include "llvm/Support/Debug.h"
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#define DEBUG_TYPE "llvm-mca"
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namespace llvm {
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namespace mca {
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RetireControlUnit::RetireControlUnit(const MCSchedModel &SM)
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: NextAvailableSlotIdx(0), CurrentInstructionSlotIdx(0),
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AvailableSlots(SM.MicroOpBufferSize), MaxRetirePerCycle(0) {
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// Check if the scheduling model provides extra information about the machine
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// processor. If so, then use that information to set the reorder buffer size
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// and the maximum number of instructions retired per cycle.
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if (SM.hasExtraProcessorInfo()) {
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const MCExtraProcessorInfo &EPI = SM.getExtraProcessorInfo();
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if (EPI.ReorderBufferSize)
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AvailableSlots = EPI.ReorderBufferSize;
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MaxRetirePerCycle = EPI.MaxRetirePerCycle;
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}
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assert(AvailableSlots && "Invalid reorder buffer size!");
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Queue.resize(AvailableSlots);
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}
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// Reserves a number of slots, and returns a new token.
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unsigned RetireControlUnit::reserveSlot(const InstRef &IR,
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unsigned NumMicroOps) {
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assert(isAvailable(NumMicroOps) && "Reorder Buffer unavailable!");
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unsigned NormalizedQuantity =
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std::min(NumMicroOps, static_cast<unsigned>(Queue.size()));
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// Zero latency instructions may have zero uOps. Artificially bump this
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// value to 1. Although zero latency instructions don't consume scheduler
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// resources, they still consume one slot in the retire queue.
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NormalizedQuantity = std::max(NormalizedQuantity, 1U);
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unsigned TokenID = NextAvailableSlotIdx;
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Queue[NextAvailableSlotIdx] = {IR, NormalizedQuantity, false};
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NextAvailableSlotIdx += NormalizedQuantity;
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NextAvailableSlotIdx %= Queue.size();
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AvailableSlots -= NormalizedQuantity;
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return TokenID;
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}
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const RetireControlUnit::RUToken &RetireControlUnit::peekCurrentToken() const {
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return Queue[CurrentInstructionSlotIdx];
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}
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void RetireControlUnit::consumeCurrentToken() {
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RetireControlUnit::RUToken &Current = Queue[CurrentInstructionSlotIdx];
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assert(Current.NumSlots && "Reserved zero slots?");
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assert(Current.IR && "Invalid RUToken in the RCU queue.");
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Current.IR.getInstruction()->retire();
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// Update the slot index to be the next item in the circular queue.
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CurrentInstructionSlotIdx += Current.NumSlots;
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CurrentInstructionSlotIdx %= Queue.size();
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AvailableSlots += Current.NumSlots;
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}
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void RetireControlUnit::onInstructionExecuted(unsigned TokenID) {
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assert(Queue.size() > TokenID);
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assert(Queue[TokenID].Executed == false && Queue[TokenID].IR);
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Queue[TokenID].Executed = true;
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}
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#ifndef NDEBUG
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void RetireControlUnit::dump() const {
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dbgs() << "Retire Unit: { Total Slots=" << Queue.size()
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<< ", Available Slots=" << AvailableSlots << " }\n";
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}
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#endif
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} // namespace mca
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} // namespace llvm
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