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578e182f73
The implementation of the xvtlsbb builtins/intrinsics were not correct as the intrinsics previously used i1 as an argument type. This patch changes the i1 argument type used in these intrinsics to be i32 instead, as having the second as an i1 can lead to issues in the backend. Differential Revision: https://reviews.llvm.org/D84291
39 lines
1.3 KiB
LLVM
39 lines
1.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O0 \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s
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; These test cases aims to test the builtins for the Power10 VSX vector
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; instructions introduced in ISA 3.1.
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declare i32 @llvm.ppc.vsx.xvtlsbb(<16 x i8>, i32)
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define signext i32 @test_vec_test_lsbb_all_ones(<16 x i8> %vuca) {
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; CHECK-LABEL: test_vec_test_lsbb_all_ones:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvtlsbb cr0, v2
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; CHECK-NEXT: mfocrf r3, 128
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; CHECK-NEXT: srwi r3, r3, 31
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; CHECK-NEXT: extsw r3, r3
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; CHECK-NEXT: blr
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entry:
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%0 = tail call i32 @llvm.ppc.vsx.xvtlsbb(<16 x i8> %vuca, i32 1)
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ret i32 %0
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}
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define signext i32 @test_vec_test_lsbb_all_zeros(<16 x i8> %vuca) {
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; CHECK-LABEL: test_vec_test_lsbb_all_zeros:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvtlsbb cr0, v2
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; CHECK-NEXT: mfocrf r3, 128
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; CHECK-NEXT: rlwinm r3, r3, 3, 31, 31
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; CHECK-NEXT: extsw r3, r3
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; CHECK-NEXT: blr
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entry:
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%0 = tail call i32 @llvm.ppc.vsx.xvtlsbb(<16 x i8> %vuca, i32 0)
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ret i32 %0
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}
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