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f50d87eb50
The algorithm it used before wasn't 100% correct, we now use an iterative expansion model. This fixes assembler errors when compiling 403.gcc with tail merging enabled. Change the way the branch selector works overall: Now, the isel generates PPC::BCC instructions (as it used to) directly, and these BCC instructions are emitted to the output or jitted directly if branches don't need expansion. Only if branches need expansion are instructions rewritten and created. This should make branch select faster, and eliminates the Bxx instructions from the .td file. llvm-svn: 31837
555 lines
14 KiB
Plaintext
555 lines
14 KiB
Plaintext
//===- README.txt - Notes for improving PowerPC-specific code gen ---------===//
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TODO:
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* gpr0 allocation
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* implement do-loop -> bdnz transform
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===-------------------------------------------------------------------------===
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Support 'update' load/store instructions. These are cracked on the G5, but are
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still a codesize win.
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With preinc enabled, this:
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long *%test4(long *%X, long *%dest) {
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%Y = getelementptr long* %X, int 4
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%A = load long* %Y
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store long %A, long* %dest
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ret long* %Y
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}
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compiles to:
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_test4:
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mr r2, r3
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lwzu r5, 32(r2)
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lwz r3, 36(r3)
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stw r5, 0(r4)
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stw r3, 4(r4)
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mr r3, r2
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blr
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with -sched=list-burr, I get:
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_test4:
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lwz r2, 36(r3)
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lwzu r5, 32(r3)
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stw r2, 4(r4)
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stw r5, 0(r4)
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blr
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===-------------------------------------------------------------------------===
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We compile the hottest inner loop of viterbi to:
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li r6, 0
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b LBB1_84 ;bb432.i
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LBB1_83: ;bb420.i
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lbzx r8, r5, r7
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addi r6, r7, 1
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stbx r8, r4, r7
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LBB1_84: ;bb432.i
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mr r7, r6
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cmplwi cr0, r7, 143
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bne cr0, LBB1_83 ;bb420.i
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The CBE manages to produce:
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li r0, 143
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mtctr r0
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loop:
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lbzx r2, r2, r11
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stbx r0, r2, r9
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addi r2, r2, 1
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bdz later
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b loop
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This could be much better (bdnz instead of bdz) but it still beats us. If we
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produced this with bdnz, the loop would be a single dispatch group.
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===-------------------------------------------------------------------------===
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Compile:
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void foo(int *P) {
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if (P) *P = 0;
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}
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into:
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_foo:
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cmpwi cr0,r3,0
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beqlr cr0
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li r0,0
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stw r0,0(r3)
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blr
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This is effectively a simple form of predication.
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===-------------------------------------------------------------------------===
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Lump the constant pool for each function into ONE pic object, and reference
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pieces of it as offsets from the start. For functions like this (contrived
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to have lots of constants obviously):
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double X(double Y) { return (Y*1.23 + 4.512)*2.34 + 14.38; }
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We generate:
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_X:
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lis r2, ha16(.CPI_X_0)
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lfd f0, lo16(.CPI_X_0)(r2)
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lis r2, ha16(.CPI_X_1)
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lfd f2, lo16(.CPI_X_1)(r2)
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fmadd f0, f1, f0, f2
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lis r2, ha16(.CPI_X_2)
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lfd f1, lo16(.CPI_X_2)(r2)
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lis r2, ha16(.CPI_X_3)
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lfd f2, lo16(.CPI_X_3)(r2)
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fmadd f1, f0, f1, f2
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blr
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It would be better to materialize .CPI_X into a register, then use immediates
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off of the register to avoid the lis's. This is even more important in PIC
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mode.
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Note that this (and the static variable version) is discussed here for GCC:
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http://gcc.gnu.org/ml/gcc-patches/2006-02/msg00133.html
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===-------------------------------------------------------------------------===
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PIC Code Gen IPO optimization:
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Squish small scalar globals together into a single global struct, allowing the
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address of the struct to be CSE'd, avoiding PIC accesses (also reduces the size
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of the GOT on targets with one).
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Note that this is discussed here for GCC:
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http://gcc.gnu.org/ml/gcc-patches/2006-02/msg00133.html
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===-------------------------------------------------------------------------===
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Implement Newton-Rhapson method for improving estimate instructions to the
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correct accuracy, and implementing divide as multiply by reciprocal when it has
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more than one use. Itanium will want this too.
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===-------------------------------------------------------------------------===
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Compile this:
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int %f1(int %a, int %b) {
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%tmp.1 = and int %a, 15 ; <int> [#uses=1]
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%tmp.3 = and int %b, 240 ; <int> [#uses=1]
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%tmp.4 = or int %tmp.3, %tmp.1 ; <int> [#uses=1]
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ret int %tmp.4
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}
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without a copy. We make this currently:
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_f1:
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rlwinm r2, r4, 0, 24, 27
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rlwimi r2, r3, 0, 28, 31
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or r3, r2, r2
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blr
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The two-addr pass or RA needs to learn when it is profitable to commute an
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instruction to avoid a copy AFTER the 2-addr instruction. The 2-addr pass
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currently only commutes to avoid inserting a copy BEFORE the two addr instr.
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===-------------------------------------------------------------------------===
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Compile offsets from allocas:
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int *%test() {
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%X = alloca { int, int }
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%Y = getelementptr {int,int}* %X, int 0, uint 1
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ret int* %Y
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}
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into a single add, not two:
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_test:
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addi r2, r1, -8
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addi r3, r2, 4
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blr
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--> important for C++.
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===-------------------------------------------------------------------------===
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No loads or stores of the constants should be needed:
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struct foo { double X, Y; };
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void xxx(struct foo F);
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void bar() { struct foo R = { 1.0, 2.0 }; xxx(R); }
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===-------------------------------------------------------------------------===
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Darwin Stub LICM optimization:
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Loops like this:
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for (...) bar();
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Have to go through an indirect stub if bar is external or linkonce. It would
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be better to compile it as:
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fp = &bar;
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for (...) fp();
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which only computes the address of bar once (instead of each time through the
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stub). This is Darwin specific and would have to be done in the code generator.
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Probably not a win on x86.
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===-------------------------------------------------------------------------===
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Simple IPO for argument passing, change:
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void foo(int X, double Y, int Z) -> void foo(int X, int Z, double Y)
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the Darwin ABI specifies that any integer arguments in the first 32 bytes worth
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of arguments get assigned to r3 through r10. That is, if you have a function
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foo(int, double, int) you get r3, f1, r6, since the 64 bit double ate up the
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argument bytes for r4 and r5. The trick then would be to shuffle the argument
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order for functions we can internalize so that the maximum number of
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integers/pointers get passed in regs before you see any of the fp arguments.
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Instead of implementing this, it would actually probably be easier to just
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implement a PPC fastcc, where we could do whatever we wanted to the CC,
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including having this work sanely.
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===-------------------------------------------------------------------------===
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Fix Darwin FP-In-Integer Registers ABI
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Darwin passes doubles in structures in integer registers, which is very very
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bad. Add something like a BIT_CONVERT to LLVM, then do an i-p transformation
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that percolates these things out of functions.
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Check out how horrible this is:
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http://gcc.gnu.org/ml/gcc/2005-10/msg01036.html
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This is an extension of "interprocedural CC unmunging" that can't be done with
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just fastcc.
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===-------------------------------------------------------------------------===
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Compile this:
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int foo(int a) {
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int b = (a < 8);
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if (b) {
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return b * 3; // ignore the fact that this is always 3.
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} else {
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return 2;
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}
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}
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into something not this:
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_foo:
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1) cmpwi cr7, r3, 8
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mfcr r2, 1
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rlwinm r2, r2, 29, 31, 31
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1) cmpwi cr0, r3, 7
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bgt cr0, LBB1_2 ; UnifiedReturnBlock
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LBB1_1: ; then
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rlwinm r2, r2, 0, 31, 31
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mulli r3, r2, 3
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blr
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LBB1_2: ; UnifiedReturnBlock
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li r3, 2
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blr
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In particular, the two compares (marked 1) could be shared by reversing one.
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This could be done in the dag combiner, by swapping a BR_CC when a SETCC of the
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same operands (but backwards) exists. In this case, this wouldn't save us
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anything though, because the compares still wouldn't be shared.
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===-------------------------------------------------------------------------===
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The legalizer should lower this:
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bool %test(ulong %x) {
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%tmp = setlt ulong %x, 4294967296
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ret bool %tmp
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}
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into "if x.high == 0", not:
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_test:
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addi r2, r3, -1
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cntlzw r2, r2
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cntlzw r3, r3
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srwi r2, r2, 5
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srwi r4, r3, 5
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li r3, 0
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cmpwi cr0, r2, 0
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bne cr0, LBB1_2 ;
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LBB1_1:
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or r3, r4, r4
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LBB1_2:
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blr
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noticed in 2005-05-11-Popcount-ffs-fls.c.
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===-------------------------------------------------------------------------===
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We should custom expand setcc instead of pretending that we have it. That
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would allow us to expose the access of the crbit after the mfcr, allowing
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that access to be trivially folded into other ops. A simple example:
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int foo(int a, int b) { return (a < b) << 4; }
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compiles into:
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_foo:
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cmpw cr7, r3, r4
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mfcr r2, 1
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rlwinm r2, r2, 29, 31, 31
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slwi r3, r2, 4
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blr
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===-------------------------------------------------------------------------===
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Fold add and sub with constant into non-extern, non-weak addresses so this:
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static int a;
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void bar(int b) { a = b; }
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void foo(unsigned char *c) {
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*c = a;
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}
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So that
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_foo:
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lis r2, ha16(_a)
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la r2, lo16(_a)(r2)
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lbz r2, 3(r2)
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stb r2, 0(r3)
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blr
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Becomes
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_foo:
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lis r2, ha16(_a+3)
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lbz r2, lo16(_a+3)(r2)
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stb r2, 0(r3)
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blr
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===-------------------------------------------------------------------------===
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We generate really bad code for this:
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int f(signed char *a, _Bool b, _Bool c) {
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signed char t = 0;
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if (b) t = *a;
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if (c) *a = t;
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}
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===-------------------------------------------------------------------------===
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This:
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int test(unsigned *P) { return *P >> 24; }
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Should compile to:
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_test:
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lbz r3,0(r3)
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blr
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not:
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_test:
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lwz r2, 0(r3)
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srwi r3, r2, 24
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blr
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===-------------------------------------------------------------------------===
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On the G5, logical CR operations are more expensive in their three
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address form: ops that read/write the same register are half as expensive as
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those that read from two registers that are different from their destination.
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We should model this with two separate instructions. The isel should generate
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the "two address" form of the instructions. When the register allocator
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detects that it needs to insert a copy due to the two-addresness of the CR
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logical op, it will invoke PPCInstrInfo::convertToThreeAddress. At this point
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we can convert to the "three address" instruction, to save code space.
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This only matters when we start generating cr logical ops.
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===-------------------------------------------------------------------------===
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We should compile these two functions to the same thing:
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#include <stdlib.h>
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void f(int a, int b, int *P) {
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*P = (a-b)>=0?(a-b):(b-a);
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}
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void g(int a, int b, int *P) {
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*P = abs(a-b);
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}
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Further, they should compile to something better than:
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_g:
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subf r2, r4, r3
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subfic r3, r2, 0
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cmpwi cr0, r2, -1
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bgt cr0, LBB2_2 ; entry
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LBB2_1: ; entry
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mr r2, r3
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LBB2_2: ; entry
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stw r2, 0(r5)
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blr
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GCC produces:
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_g:
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subf r4,r4,r3
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srawi r2,r4,31
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xor r0,r2,r4
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subf r0,r2,r0
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stw r0,0(r5)
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blr
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... which is much nicer.
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This theoretically may help improve twolf slightly (used in dimbox.c:142?).
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===-------------------------------------------------------------------------===
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int foo(int N, int ***W, int **TK, int X) {
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int t, i;
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for (t = 0; t < N; ++t)
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for (i = 0; i < 4; ++i)
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W[t / X][i][t % X] = TK[i][t];
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return 5;
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}
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We generate relatively atrocious code for this loop compared to gcc.
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We could also strength reduce the rem and the div:
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http://www.lcs.mit.edu/pubs/pdf/MIT-LCS-TM-600.pdf
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===-------------------------------------------------------------------------===
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float foo(float X) { return (int)(X); }
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Currently produces:
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_foo:
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fctiwz f0, f1
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stfd f0, -8(r1)
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lwz r2, -4(r1)
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extsw r2, r2
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std r2, -16(r1)
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lfd f0, -16(r1)
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fcfid f0, f0
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frsp f1, f0
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blr
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We could use a target dag combine to turn the lwz/extsw into an lwa when the
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lwz has a single use. Since LWA is cracked anyway, this would be a codesize
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win only.
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===-------------------------------------------------------------------------===
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We generate ugly code for this:
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void func(unsigned int *ret, float dx, float dy, float dz, float dw) {
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unsigned code = 0;
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if(dx < -dw) code |= 1;
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if(dx > dw) code |= 2;
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if(dy < -dw) code |= 4;
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if(dy > dw) code |= 8;
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if(dz < -dw) code |= 16;
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if(dz > dw) code |= 32;
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*ret = code;
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}
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===-------------------------------------------------------------------------===
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Complete the signed i32 to FP conversion code using 64-bit registers
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transformation, good for PI. See PPCISelLowering.cpp, this comment:
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// FIXME: disable this lowered code. This generates 64-bit register values,
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// and we don't model the fact that the top part is clobbered by calls. We
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// need to flag these together so that the value isn't live across a call.
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//setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
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Also, if the registers are spilled to the stack, we have to ensure that all
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64-bits of them are save/restored, otherwise we will miscompile the code. It
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sounds like we need to get the 64-bit register classes going.
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===-------------------------------------------------------------------------===
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%struct.B = type { ubyte, [3 x ubyte] }
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void %foo(%struct.B* %b) {
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entry:
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%tmp = cast %struct.B* %b to uint* ; <uint*> [#uses=1]
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%tmp = load uint* %tmp ; <uint> [#uses=1]
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%tmp3 = cast %struct.B* %b to uint* ; <uint*> [#uses=1]
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%tmp4 = load uint* %tmp3 ; <uint> [#uses=1]
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%tmp8 = cast %struct.B* %b to uint* ; <uint*> [#uses=2]
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%tmp9 = load uint* %tmp8 ; <uint> [#uses=1]
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%tmp4.mask17 = shl uint %tmp4, ubyte 1 ; <uint> [#uses=1]
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%tmp1415 = and uint %tmp4.mask17, 2147483648 ; <uint> [#uses=1]
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%tmp.masked = and uint %tmp, 2147483648 ; <uint> [#uses=1]
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%tmp11 = or uint %tmp1415, %tmp.masked ; <uint> [#uses=1]
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%tmp12 = and uint %tmp9, 2147483647 ; <uint> [#uses=1]
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%tmp13 = or uint %tmp12, %tmp11 ; <uint> [#uses=1]
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store uint %tmp13, uint* %tmp8
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ret void
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}
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We emit:
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_foo:
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lwz r2, 0(r3)
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slwi r4, r2, 1
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or r4, r4, r2
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rlwimi r2, r4, 0, 0, 0
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stw r2, 0(r3)
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blr
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We could collapse a bunch of those ORs and ANDs and generate the following
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equivalent code:
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_foo:
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lwz r2, 0(r3)
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rlwinm r4, r2, 1, 0, 0
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or r2, r2, r4
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stw r2, 0(r3)
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blr
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===-------------------------------------------------------------------------===
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We compile:
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unsigned test6(unsigned x) {
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return ((x & 0x00FF0000) >> 16) | ((x & 0x000000FF) << 16);
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}
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into:
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_test6:
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lis r2, 255
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rlwinm r3, r3, 16, 0, 31
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ori r2, r2, 255
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and r3, r3, r2
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blr
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GCC gets it down to:
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_test6:
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rlwinm r0,r3,16,8,15
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rlwinm r3,r3,16,24,31
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or r3,r3,r0
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blr
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