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e13811edf1
SystemZExpandPseudo:s only job was to expand LOCRMux instructions into jump sequences. This needs to be done if expandLOCRPseudo() or expandSELRPseudo() fails to find a legal opcode (all registers "high" or "low"). This task has now been moved to SystemZPostRewrite while removing the SystemZExpandPseudo pass. It is in fact preferred to expand these pseudos directly after register allocation in SystemZPostRewrite since the hinted register combinations are then not subject to later optimizations. Review: Ulrich Weigand https://reviews.llvm.org/D67432 llvm-svn: 371959
338 lines
13 KiB
C++
338 lines
13 KiB
C++
//===-- SystemZInstrInfo.h - SystemZ instruction information ----*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the SystemZ implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H
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#define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H
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#include "SystemZ.h"
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#include "SystemZRegisterInfo.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include <cstdint>
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#define GET_INSTRINFO_HEADER
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#include "SystemZGenInstrInfo.inc"
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namespace llvm {
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class SystemZSubtarget;
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namespace SystemZII {
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enum {
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// See comments in SystemZInstrFormats.td.
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SimpleBDXLoad = (1 << 0),
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SimpleBDXStore = (1 << 1),
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Has20BitOffset = (1 << 2),
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HasIndex = (1 << 3),
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Is128Bit = (1 << 4),
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AccessSizeMask = (31 << 5),
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AccessSizeShift = 5,
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CCValuesMask = (15 << 10),
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CCValuesShift = 10,
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CompareZeroCCMaskMask = (15 << 14),
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CompareZeroCCMaskShift = 14,
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CCMaskFirst = (1 << 18),
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CCMaskLast = (1 << 19),
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IsLogical = (1 << 20)
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};
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static inline unsigned getAccessSize(unsigned int Flags) {
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return (Flags & AccessSizeMask) >> AccessSizeShift;
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}
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static inline unsigned getCCValues(unsigned int Flags) {
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return (Flags & CCValuesMask) >> CCValuesShift;
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}
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static inline unsigned getCompareZeroCCMask(unsigned int Flags) {
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return (Flags & CompareZeroCCMaskMask) >> CompareZeroCCMaskShift;
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}
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// SystemZ MachineOperand target flags.
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enum {
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// Masks out the bits for the access model.
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MO_SYMBOL_MODIFIER = (3 << 0),
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// @GOT (aka @GOTENT)
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MO_GOT = (1 << 0),
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// @INDNTPOFF
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MO_INDNTPOFF = (2 << 0)
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};
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// Classifies a branch.
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enum BranchType {
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// An instruction that branches on the current value of CC.
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BranchNormal,
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// An instruction that peforms a 32-bit signed comparison and branches
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// on the result.
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BranchC,
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// An instruction that peforms a 32-bit unsigned comparison and branches
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// on the result.
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BranchCL,
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// An instruction that peforms a 64-bit signed comparison and branches
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// on the result.
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BranchCG,
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// An instruction that peforms a 64-bit unsigned comparison and branches
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// on the result.
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BranchCLG,
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// An instruction that decrements a 32-bit register and branches if
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// the result is nonzero.
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BranchCT,
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// An instruction that decrements a 64-bit register and branches if
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// the result is nonzero.
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BranchCTG,
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// An instruction representing an asm goto statement.
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AsmGoto
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};
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// Information about a branch instruction.
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class Branch {
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// The target of the branch. In case of INLINEASM_BR, this is nullptr.
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const MachineOperand *Target;
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public:
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// The type of the branch.
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BranchType Type;
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// CCMASK_<N> is set if CC might be equal to N.
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unsigned CCValid;
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// CCMASK_<N> is set if the branch should be taken when CC == N.
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unsigned CCMask;
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Branch(BranchType type, unsigned ccValid, unsigned ccMask,
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const MachineOperand *target)
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: Target(target), Type(type), CCValid(ccValid), CCMask(ccMask) {}
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bool isIndirect() { return Target != nullptr && Target->isReg(); }
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bool hasMBBTarget() { return Target != nullptr && Target->isMBB(); }
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MachineBasicBlock *getMBBTarget() {
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return hasMBBTarget() ? Target->getMBB() : nullptr;
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}
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};
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// Kinds of fused compares in compare-and-* instructions. Together with type
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// of the converted compare, this identifies the compare-and-*
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// instruction.
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enum FusedCompareType {
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// Relative branch - CRJ etc.
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CompareAndBranch,
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// Indirect branch, used for return - CRBReturn etc.
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CompareAndReturn,
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// Indirect branch, used for sibcall - CRBCall etc.
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CompareAndSibcall,
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// Trap
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CompareAndTrap
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};
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} // end namespace SystemZII
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namespace SystemZ {
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int getTwoOperandOpcode(uint16_t Opcode);
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int getTargetMemOpcode(uint16_t Opcode);
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}
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class SystemZInstrInfo : public SystemZGenInstrInfo {
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const SystemZRegisterInfo RI;
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SystemZSubtarget &STI;
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void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const;
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void splitAdjDynAlloc(MachineBasicBlock::iterator MI) const;
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void expandRIPseudo(MachineInstr &MI, unsigned LowOpcode, unsigned HighOpcode,
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bool ConvertHigh) const;
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void expandRIEPseudo(MachineInstr &MI, unsigned LowOpcode,
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unsigned LowOpcodeK, unsigned HighOpcode) const;
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void expandRXYPseudo(MachineInstr &MI, unsigned LowOpcode,
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unsigned HighOpcode) const;
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void expandLOCPseudo(MachineInstr &MI, unsigned LowOpcode,
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unsigned HighOpcode) const;
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void expandZExtPseudo(MachineInstr &MI, unsigned LowOpcode,
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unsigned Size) const;
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void expandLoadStackGuard(MachineInstr *MI) const;
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MachineInstrBuilder
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emitGRX32Move(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
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unsigned LowLowOpcode, unsigned Size, bool KillSrc,
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bool UndefSrc) const;
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virtual void anchor();
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protected:
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/// Commutes the operands in the given instruction by changing the operands
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/// order and/or changing the instruction's opcode and/or the immediate value
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/// operand.
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///
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/// The arguments 'CommuteOpIdx1' and 'CommuteOpIdx2' specify the operands
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/// to be commuted.
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///
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/// Do not call this method for a non-commutable instruction or
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/// non-commutable operands.
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/// Even though the instruction is commutable, the method may still
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/// fail to commute the operands, null pointer is returned in such cases.
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MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
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unsigned CommuteOpIdx1,
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unsigned CommuteOpIdx2) const override;
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public:
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explicit SystemZInstrInfo(SystemZSubtarget &STI);
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// Override TargetInstrInfo.
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unsigned isLoadFromStackSlot(const MachineInstr &MI,
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int &FrameIndex) const override;
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unsigned isStoreToStackSlot(const MachineInstr &MI,
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int &FrameIndex) const override;
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bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex,
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int &SrcFrameIndex) const override;
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bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const override;
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unsigned removeBranch(MachineBasicBlock &MBB,
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int *BytesRemoved = nullptr) const override;
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unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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const DebugLoc &DL,
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int *BytesAdded = nullptr) const override;
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bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
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unsigned &SrcReg2, int &Mask, int &Value) const override;
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bool canInsertSelect(const MachineBasicBlock&, ArrayRef<MachineOperand> Cond,
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unsigned, unsigned, int&, int&, int&) const override;
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void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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const DebugLoc &DL, unsigned DstReg,
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ArrayRef<MachineOperand> Cond, unsigned TrueReg,
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unsigned FalseReg) const override;
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bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg,
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MachineRegisterInfo *MRI) const override;
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bool isPredicable(const MachineInstr &MI) const override;
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bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
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unsigned ExtraPredCycles,
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BranchProbability Probability) const override;
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bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
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unsigned NumCyclesT, unsigned ExtraPredCyclesT,
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MachineBasicBlock &FMBB,
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unsigned NumCyclesF, unsigned ExtraPredCyclesF,
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BranchProbability Probability) const override;
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bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
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BranchProbability Probability) const override;
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bool PredicateInstruction(MachineInstr &MI,
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ArrayRef<MachineOperand> Pred) const override;
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void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const override;
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void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned DestReg, int FrameIdx,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
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MachineInstr &MI,
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LiveVariables *LV) const override;
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MachineInstr *
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foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
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ArrayRef<unsigned> Ops,
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MachineBasicBlock::iterator InsertPt, int FrameIndex,
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LiveIntervals *LIS = nullptr,
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VirtRegMap *VRM = nullptr) const override;
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MachineInstr *foldMemoryOperandImpl(
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MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
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MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
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LiveIntervals *LIS = nullptr) const override;
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bool expandPostRAPseudo(MachineInstr &MBBI) const override;
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bool reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
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override;
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// Return the SystemZRegisterInfo, which this class owns.
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const SystemZRegisterInfo &getRegisterInfo() const { return RI; }
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// Return the size in bytes of MI.
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unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
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// Return true if MI is a conditional or unconditional branch.
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// When returning true, set Cond to the mask of condition-code
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// values on which the instruction will branch, and set Target
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// to the operand that contains the branch target. This target
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// can be a register or a basic block.
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SystemZII::Branch getBranchInfo(const MachineInstr &MI) const;
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// Get the load and store opcodes for a given register class.
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void getLoadStoreOpcodes(const TargetRegisterClass *RC,
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unsigned &LoadOpcode, unsigned &StoreOpcode) const;
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// Opcode is the opcode of an instruction that has an address operand,
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// and the caller wants to perform that instruction's operation on an
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// address that has displacement Offset. Return the opcode of a suitable
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// instruction (which might be Opcode itself) or 0 if no such instruction
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// exists.
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unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset) const;
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// If Opcode is a load instruction that has a LOAD AND TEST form,
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// return the opcode for the testing form, otherwise return 0.
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unsigned getLoadAndTest(unsigned Opcode) const;
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// Return true if ROTATE AND ... SELECTED BITS can be used to select bits
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// Mask of the R2 operand, given that only the low BitSize bits of Mask are
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// significant. Set Start and End to the I3 and I4 operands if so.
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bool isRxSBGMask(uint64_t Mask, unsigned BitSize,
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unsigned &Start, unsigned &End) const;
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// If Opcode is a COMPARE opcode for which an associated fused COMPARE AND *
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// operation exists, return the opcode for the latter, otherwise return 0.
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// MI, if nonnull, is the compare instruction.
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unsigned getFusedCompare(unsigned Opcode,
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SystemZII::FusedCompareType Type,
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const MachineInstr *MI = nullptr) const;
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// If Opcode is a LOAD opcode for with an associated LOAD AND TRAP
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// operation exists, returh the opcode for the latter, otherwise return 0.
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unsigned getLoadAndTrap(unsigned Opcode) const;
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// Emit code before MBBI in MI to move immediate value Value into
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// physical register Reg.
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void loadImmediate(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned Reg, uint64_t Value) const;
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// Sometimes, it is possible for the target to tell, even without
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// aliasing information, that two MIs access different memory
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// addresses. This function returns true if two MIs access different
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// memory addresses and false otherwise.
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bool
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areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
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const MachineInstr &MIb,
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AliasAnalysis *AA = nullptr) const override;
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H
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