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to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
179 lines
7.6 KiB
C++
179 lines
7.6 KiB
C++
//==- HexagonFrameLowering.h - Define frame lowering for Hexagon -*- C++ -*-==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONFRAMELOWERING_H
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#define LLVM_LIB_TARGET_HEXAGON_HEXAGONFRAMELOWERING_H
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#include "Hexagon.h"
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#include "HexagonBlockRanges.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/TargetFrameLowering.h"
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#include <vector>
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namespace llvm {
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class BitVector;
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class HexagonInstrInfo;
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class HexagonRegisterInfo;
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class MachineFunction;
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class MachineInstr;
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class MachineRegisterInfo;
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class TargetRegisterClass;
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class HexagonFrameLowering : public TargetFrameLowering {
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public:
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explicit HexagonFrameLowering()
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: TargetFrameLowering(StackGrowsDown, 8, 0, 1, true) {}
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// All of the prolog/epilog functionality, including saving and restoring
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// callee-saved registers is handled in emitPrologue. This is to have the
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// logic for shrink-wrapping in one place.
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void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const
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override;
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void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
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override {}
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bool enableCalleeSaveSkip(const MachineFunction &MF) const override;
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bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const override {
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return true;
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}
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bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const override {
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return true;
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}
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bool hasReservedCallFrame(const MachineFunction &MF) const override {
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// We always reserve call frame as a part of the initial stack allocation.
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return true;
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}
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bool canSimplifyCallFramePseudos(const MachineFunction &MF) const override {
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// Override this function to avoid calling hasFP before CSI is set
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// (the default implementation calls hasFP).
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return true;
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}
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MachineBasicBlock::iterator
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const override;
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void processFunctionBeforeFrameFinalized(MachineFunction &MF,
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RegScavenger *RS = nullptr) const override;
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void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
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RegScavenger *RS) const override;
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bool targetHandlesStackFrameRounding() const override {
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return true;
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}
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int getFrameIndexReference(const MachineFunction &MF, int FI,
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unsigned &FrameReg) const override;
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bool hasFP(const MachineFunction &MF) const override;
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const SpillSlot *getCalleeSavedSpillSlots(unsigned &NumEntries)
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const override {
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static const SpillSlot Offsets[] = {
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{ Hexagon::R17, -4 }, { Hexagon::R16, -8 }, { Hexagon::D8, -8 },
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{ Hexagon::R19, -12 }, { Hexagon::R18, -16 }, { Hexagon::D9, -16 },
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{ Hexagon::R21, -20 }, { Hexagon::R20, -24 }, { Hexagon::D10, -24 },
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{ Hexagon::R23, -28 }, { Hexagon::R22, -32 }, { Hexagon::D11, -32 },
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{ Hexagon::R25, -36 }, { Hexagon::R24, -40 }, { Hexagon::D12, -40 },
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{ Hexagon::R27, -44 }, { Hexagon::R26, -48 }, { Hexagon::D13, -48 }
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};
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NumEntries = array_lengthof(Offsets);
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return Offsets;
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}
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bool assignCalleeSavedSpillSlots(MachineFunction &MF,
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const TargetRegisterInfo *TRI, std::vector<CalleeSavedInfo> &CSI)
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const override;
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bool needsAligna(const MachineFunction &MF) const;
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const MachineInstr *getAlignaInstr(const MachineFunction &MF) const;
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void insertCFIInstructions(MachineFunction &MF) const;
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private:
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using CSIVect = std::vector<CalleeSavedInfo>;
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void expandAlloca(MachineInstr *AI, const HexagonInstrInfo &TII,
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unsigned SP, unsigned CF) const;
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void insertPrologueInBlock(MachineBasicBlock &MBB, bool PrologueStubs) const;
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void insertEpilogueInBlock(MachineBasicBlock &MBB) const;
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void insertAllocframe(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator InsertPt, unsigned NumBytes) const;
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bool insertCSRSpillsInBlock(MachineBasicBlock &MBB, const CSIVect &CSI,
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const HexagonRegisterInfo &HRI, bool &PrologueStubs) const;
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bool insertCSRRestoresInBlock(MachineBasicBlock &MBB, const CSIVect &CSI,
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const HexagonRegisterInfo &HRI) const;
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void updateEntryPaths(MachineFunction &MF, MachineBasicBlock &SaveB) const;
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bool updateExitPaths(MachineBasicBlock &MBB, MachineBasicBlock &RestoreB,
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BitVector &DoneT, BitVector &DoneF, BitVector &Path) const;
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void insertCFIInstructionsAt(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator At) const;
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void adjustForCalleeSavedRegsSpillCall(MachineFunction &MF) const;
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bool expandCopy(MachineBasicBlock &B, MachineBasicBlock::iterator It,
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MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
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SmallVectorImpl<unsigned> &NewRegs) const;
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bool expandStoreInt(MachineBasicBlock &B, MachineBasicBlock::iterator It,
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MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
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SmallVectorImpl<unsigned> &NewRegs) const;
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bool expandLoadInt(MachineBasicBlock &B, MachineBasicBlock::iterator It,
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MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
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SmallVectorImpl<unsigned> &NewRegs) const;
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bool expandStoreVecPred(MachineBasicBlock &B, MachineBasicBlock::iterator It,
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MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
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SmallVectorImpl<unsigned> &NewRegs) const;
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bool expandLoadVecPred(MachineBasicBlock &B, MachineBasicBlock::iterator It,
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MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
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SmallVectorImpl<unsigned> &NewRegs) const;
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bool expandStoreVec2(MachineBasicBlock &B, MachineBasicBlock::iterator It,
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MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
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SmallVectorImpl<unsigned> &NewRegs) const;
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bool expandLoadVec2(MachineBasicBlock &B, MachineBasicBlock::iterator It,
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MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
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SmallVectorImpl<unsigned> &NewRegs) const;
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bool expandStoreVec(MachineBasicBlock &B, MachineBasicBlock::iterator It,
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MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
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SmallVectorImpl<unsigned> &NewRegs) const;
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bool expandLoadVec(MachineBasicBlock &B, MachineBasicBlock::iterator It,
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MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
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SmallVectorImpl<unsigned> &NewRegs) const;
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bool expandSpillMacros(MachineFunction &MF,
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SmallVectorImpl<unsigned> &NewRegs) const;
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unsigned findPhysReg(MachineFunction &MF, HexagonBlockRanges::IndexRange &FIR,
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HexagonBlockRanges::InstrIndexMap &IndexMap,
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HexagonBlockRanges::RegToRangeMap &DeadMap,
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const TargetRegisterClass *RC) const;
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void optimizeSpillSlots(MachineFunction &MF,
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SmallVectorImpl<unsigned> &VRegs) const;
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void findShrunkPrologEpilog(MachineFunction &MF, MachineBasicBlock *&PrologB,
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MachineBasicBlock *&EpilogB) const;
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void addCalleeSaveRegistersAsImpOperand(MachineInstr *MI, const CSIVect &CSI,
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bool IsDef, bool IsKill) const;
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bool shouldInlineCSR(const MachineFunction &MF, const CSIVect &CSI) const;
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bool useSpillFunction(const MachineFunction &MF, const CSIVect &CSI) const;
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bool useRestoreFunction(const MachineFunction &MF, const CSIVect &CSI) const;
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bool mayOverflowFrameOffset(MachineFunction &MF) const;
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONFRAMELOWERING_H
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