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to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
341 lines
9.9 KiB
C++
341 lines
9.9 KiB
C++
//===- HexagonRDFOpt.cpp --------------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "HexagonInstrInfo.h"
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#include "HexagonSubtarget.h"
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#include "MCTargetDesc/HexagonBaseInfo.h"
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#include "RDFCopy.h"
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#include "RDFDeadCode.h"
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#include "RDFGraph.h"
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#include "RDFLiveness.h"
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#include "RDFRegisters.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SetVector.h"
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#include "llvm/CodeGen/MachineDominanceFrontier.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Pass.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include <cassert>
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#include <limits>
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#include <utility>
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using namespace llvm;
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using namespace rdf;
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namespace llvm {
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void initializeHexagonRDFOptPass(PassRegistry&);
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FunctionPass *createHexagonRDFOpt();
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} // end namespace llvm
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static unsigned RDFCount = 0;
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static cl::opt<unsigned> RDFLimit("rdf-limit",
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cl::init(std::numeric_limits<unsigned>::max()));
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static cl::opt<bool> RDFDump("rdf-dump", cl::init(false));
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namespace {
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class HexagonRDFOpt : public MachineFunctionPass {
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public:
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HexagonRDFOpt() : MachineFunctionPass(ID) {}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.addRequired<MachineDominatorTree>();
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AU.addRequired<MachineDominanceFrontier>();
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AU.setPreservesAll();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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StringRef getPassName() const override {
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return "Hexagon RDF optimizations";
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties().set(
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MachineFunctionProperties::Property::NoVRegs);
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}
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static char ID;
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private:
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MachineDominatorTree *MDT;
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MachineRegisterInfo *MRI;
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};
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struct HexagonCP : public CopyPropagation {
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HexagonCP(DataFlowGraph &G) : CopyPropagation(G) {}
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bool interpretAsCopy(const MachineInstr *MI, EqualityMap &EM) override;
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};
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struct HexagonDCE : public DeadCodeElimination {
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HexagonDCE(DataFlowGraph &G, MachineRegisterInfo &MRI)
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: DeadCodeElimination(G, MRI) {}
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bool rewrite(NodeAddr<InstrNode*> IA, SetVector<NodeId> &Remove);
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void removeOperand(NodeAddr<InstrNode*> IA, unsigned OpNum);
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bool run();
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};
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} // end anonymous namespace
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char HexagonRDFOpt::ID = 0;
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INITIALIZE_PASS_BEGIN(HexagonRDFOpt, "hexagon-rdf-opt",
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"Hexagon RDF optimizations", false, false)
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INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
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INITIALIZE_PASS_DEPENDENCY(MachineDominanceFrontier)
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INITIALIZE_PASS_END(HexagonRDFOpt, "hexagon-rdf-opt",
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"Hexagon RDF optimizations", false, false)
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bool HexagonCP::interpretAsCopy(const MachineInstr *MI, EqualityMap &EM) {
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auto mapRegs = [&EM] (RegisterRef DstR, RegisterRef SrcR) -> void {
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EM.insert(std::make_pair(DstR, SrcR));
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};
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DataFlowGraph &DFG = getDFG();
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unsigned Opc = MI->getOpcode();
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switch (Opc) {
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case Hexagon::A2_combinew: {
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const MachineOperand &DstOp = MI->getOperand(0);
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const MachineOperand &HiOp = MI->getOperand(1);
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const MachineOperand &LoOp = MI->getOperand(2);
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assert(DstOp.getSubReg() == 0 && "Unexpected subregister");
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mapRegs(DFG.makeRegRef(DstOp.getReg(), Hexagon::isub_hi),
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DFG.makeRegRef(HiOp.getReg(), HiOp.getSubReg()));
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mapRegs(DFG.makeRegRef(DstOp.getReg(), Hexagon::isub_lo),
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DFG.makeRegRef(LoOp.getReg(), LoOp.getSubReg()));
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return true;
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}
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case Hexagon::A2_addi: {
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const MachineOperand &A = MI->getOperand(2);
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if (!A.isImm() || A.getImm() != 0)
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return false;
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LLVM_FALLTHROUGH;
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}
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case Hexagon::A2_tfr: {
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const MachineOperand &DstOp = MI->getOperand(0);
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const MachineOperand &SrcOp = MI->getOperand(1);
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mapRegs(DFG.makeRegRef(DstOp.getReg(), DstOp.getSubReg()),
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DFG.makeRegRef(SrcOp.getReg(), SrcOp.getSubReg()));
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return true;
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}
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}
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return CopyPropagation::interpretAsCopy(MI, EM);
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}
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bool HexagonDCE::run() {
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bool Collected = collect();
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if (!Collected)
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return false;
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const SetVector<NodeId> &DeadNodes = getDeadNodes();
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const SetVector<NodeId> &DeadInstrs = getDeadInstrs();
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using RefToInstrMap = DenseMap<NodeId, NodeId>;
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RefToInstrMap R2I;
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SetVector<NodeId> PartlyDead;
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DataFlowGraph &DFG = getDFG();
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for (NodeAddr<BlockNode*> BA : DFG.getFunc().Addr->members(DFG)) {
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for (auto TA : BA.Addr->members_if(DFG.IsCode<NodeAttrs::Stmt>, DFG)) {
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NodeAddr<StmtNode*> SA = TA;
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for (NodeAddr<RefNode*> RA : SA.Addr->members(DFG)) {
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R2I.insert(std::make_pair(RA.Id, SA.Id));
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if (DFG.IsDef(RA) && DeadNodes.count(RA.Id))
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if (!DeadInstrs.count(SA.Id))
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PartlyDead.insert(SA.Id);
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}
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}
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}
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// Nodes to remove.
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SetVector<NodeId> Remove = DeadInstrs;
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bool Changed = false;
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for (NodeId N : PartlyDead) {
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auto SA = DFG.addr<StmtNode*>(N);
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if (trace())
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dbgs() << "Partly dead: " << *SA.Addr->getCode();
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Changed |= rewrite(SA, Remove);
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}
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return erase(Remove) || Changed;
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}
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void HexagonDCE::removeOperand(NodeAddr<InstrNode*> IA, unsigned OpNum) {
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MachineInstr *MI = NodeAddr<StmtNode*>(IA).Addr->getCode();
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auto getOpNum = [MI] (MachineOperand &Op) -> unsigned {
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for (unsigned i = 0, n = MI->getNumOperands(); i != n; ++i)
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if (&MI->getOperand(i) == &Op)
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return i;
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llvm_unreachable("Invalid operand");
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};
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DenseMap<NodeId,unsigned> OpMap;
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DataFlowGraph &DFG = getDFG();
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NodeList Refs = IA.Addr->members(DFG);
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for (NodeAddr<RefNode*> RA : Refs)
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OpMap.insert(std::make_pair(RA.Id, getOpNum(RA.Addr->getOp())));
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MI->RemoveOperand(OpNum);
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for (NodeAddr<RefNode*> RA : Refs) {
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unsigned N = OpMap[RA.Id];
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if (N < OpNum)
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RA.Addr->setRegRef(&MI->getOperand(N), DFG);
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else if (N > OpNum)
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RA.Addr->setRegRef(&MI->getOperand(N-1), DFG);
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}
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}
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bool HexagonDCE::rewrite(NodeAddr<InstrNode*> IA, SetVector<NodeId> &Remove) {
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if (!getDFG().IsCode<NodeAttrs::Stmt>(IA))
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return false;
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DataFlowGraph &DFG = getDFG();
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MachineInstr &MI = *NodeAddr<StmtNode*>(IA).Addr->getCode();
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auto &HII = static_cast<const HexagonInstrInfo&>(DFG.getTII());
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if (HII.getAddrMode(MI) != HexagonII::PostInc)
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return false;
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unsigned Opc = MI.getOpcode();
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unsigned OpNum, NewOpc;
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switch (Opc) {
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case Hexagon::L2_loadri_pi:
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NewOpc = Hexagon::L2_loadri_io;
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OpNum = 1;
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break;
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case Hexagon::L2_loadrd_pi:
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NewOpc = Hexagon::L2_loadrd_io;
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OpNum = 1;
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break;
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case Hexagon::V6_vL32b_pi:
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NewOpc = Hexagon::V6_vL32b_ai;
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OpNum = 1;
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break;
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case Hexagon::S2_storeri_pi:
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NewOpc = Hexagon::S2_storeri_io;
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OpNum = 0;
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break;
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case Hexagon::S2_storerd_pi:
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NewOpc = Hexagon::S2_storerd_io;
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OpNum = 0;
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break;
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case Hexagon::V6_vS32b_pi:
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NewOpc = Hexagon::V6_vS32b_ai;
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OpNum = 0;
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break;
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default:
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return false;
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}
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auto IsDead = [this] (NodeAddr<DefNode*> DA) -> bool {
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return getDeadNodes().count(DA.Id);
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};
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NodeList Defs;
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MachineOperand &Op = MI.getOperand(OpNum);
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for (NodeAddr<DefNode*> DA : IA.Addr->members_if(DFG.IsDef, DFG)) {
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if (&DA.Addr->getOp() != &Op)
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continue;
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Defs = DFG.getRelatedRefs(IA, DA);
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if (!llvm::all_of(Defs, IsDead))
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return false;
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break;
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}
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// Mark all nodes in Defs for removal.
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for (auto D : Defs)
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Remove.insert(D.Id);
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if (trace())
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dbgs() << "Rewriting: " << MI;
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MI.setDesc(HII.get(NewOpc));
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MI.getOperand(OpNum+2).setImm(0);
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removeOperand(IA, OpNum);
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if (trace())
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dbgs() << " to: " << MI;
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return true;
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}
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bool HexagonRDFOpt::runOnMachineFunction(MachineFunction &MF) {
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if (skipFunction(MF.getFunction()))
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return false;
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if (RDFLimit.getPosition()) {
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if (RDFCount >= RDFLimit)
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return false;
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RDFCount++;
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}
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MDT = &getAnalysis<MachineDominatorTree>();
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const auto &MDF = getAnalysis<MachineDominanceFrontier>();
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const auto &HII = *MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
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const auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
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MRI = &MF.getRegInfo();
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bool Changed;
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if (RDFDump)
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MF.print(dbgs() << "Before " << getPassName() << "\n", nullptr);
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TargetOperandInfo TOI(HII);
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DataFlowGraph G(MF, HII, HRI, *MDT, MDF, TOI);
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// Dead phi nodes are necessary for copy propagation: we can add a use
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// of a register in a block where it would need a phi node, but which
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// was dead (and removed) during the graph build time.
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G.build(BuildOptions::KeepDeadPhis);
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if (RDFDump)
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dbgs() << "Starting copy propagation on: " << MF.getName() << '\n'
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<< PrintNode<FuncNode*>(G.getFunc(), G) << '\n';
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HexagonCP CP(G);
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CP.trace(RDFDump);
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Changed = CP.run();
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if (RDFDump)
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dbgs() << "Starting dead code elimination on: " << MF.getName() << '\n'
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<< PrintNode<FuncNode*>(G.getFunc(), G) << '\n';
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HexagonDCE DCE(G, *MRI);
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DCE.trace(RDFDump);
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Changed |= DCE.run();
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if (Changed) {
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if (RDFDump)
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dbgs() << "Starting liveness recomputation on: " << MF.getName() << '\n';
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Liveness LV(*MRI, G);
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LV.trace(RDFDump);
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LV.computeLiveIns();
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LV.resetLiveIns();
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LV.resetKills();
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}
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if (RDFDump)
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MF.print(dbgs() << "After " << getPassName() << "\n", nullptr);
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return false;
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}
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FunctionPass *llvm::createHexagonRDFOpt() {
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return new HexagonRDFOpt();
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}
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