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624 lines
24 KiB
TableGen
624 lines
24 KiB
TableGen
//===-- SystemZOperands.td - SystemZ instruction operands ----*- tblgen-*--===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Class definitions
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//===----------------------------------------------------------------------===//
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class ImmediateAsmOperand<string name>
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: AsmOperandClass {
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let Name = name;
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let RenderMethod = "addImmOperands";
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}
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class ImmediateTLSAsmOperand<string name>
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: AsmOperandClass {
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let Name = name;
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let RenderMethod = "addImmTLSOperands";
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}
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// Constructs both a DAG pattern and instruction operand for an immediate
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// of type VT. PRED returns true if a node is acceptable and XFORM returns
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// the operand value associated with the node. ASMOP is the name of the
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// associated asm operand, and also forms the basis of the asm print method.
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class Immediate<ValueType vt, code pred, SDNodeXForm xform, string asmop>
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: PatLeaf<(vt imm), pred, xform>, Operand<vt> {
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let PrintMethod = "print"##asmop##"Operand";
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let DecoderMethod = "decode"##asmop##"Operand";
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let ParserMatchClass = !cast<AsmOperandClass>(asmop);
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}
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// Constructs an asm operand for a PC-relative address. SIZE says how
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// many bits there are.
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class PCRelAsmOperand<string size> : ImmediateAsmOperand<"PCRel"##size> {
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let PredicateMethod = "isImm";
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let ParserMethod = "parsePCRel"##size;
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}
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class PCRelTLSAsmOperand<string size>
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: ImmediateTLSAsmOperand<"PCRelTLS"##size> {
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let PredicateMethod = "isImmTLS";
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let ParserMethod = "parsePCRelTLS"##size;
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}
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// Constructs an operand for a PC-relative address with address type VT.
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// ASMOP is the associated asm operand.
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class PCRelOperand<ValueType vt, AsmOperandClass asmop> : Operand<vt> {
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let PrintMethod = "printPCRelOperand";
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let ParserMatchClass = asmop;
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}
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class PCRelTLSOperand<ValueType vt, AsmOperandClass asmop> : Operand<vt> {
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let PrintMethod = "printPCRelTLSOperand";
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let ParserMatchClass = asmop;
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}
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// Constructs both a DAG pattern and instruction operand for a PC-relative
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// address with address size VT. SELF is the name of the operand and
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// ASMOP is the associated asm operand.
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class PCRelAddress<ValueType vt, string self, AsmOperandClass asmop>
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: ComplexPattern<vt, 1, "selectPCRelAddress",
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[z_pcrel_wrapper, z_pcrel_offset]>,
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PCRelOperand<vt, asmop> {
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let MIOperandInfo = (ops !cast<Operand>(self));
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}
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// Constructs an AsmOperandClass for addressing mode FORMAT, treating the
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// registers as having BITSIZE bits and displacements as having DISPSIZE bits.
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// LENGTH is "LenN" for addresses with an N-bit length field, otherwise it
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// is "".
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class AddressAsmOperand<string format, string bitsize, string dispsize,
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string length = "">
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: AsmOperandClass {
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let Name = format##bitsize##"Disp"##dispsize##length;
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let ParserMethod = "parse"##format##bitsize;
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let RenderMethod = "add"##format##"Operands";
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}
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// Constructs an instruction operand for an addressing mode. FORMAT,
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// BITSIZE, DISPSIZE and LENGTH are the parameters to an associated
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// AddressAsmOperand. OPERANDS is a list of individual operands
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// (base register, displacement, etc.).
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class AddressOperand<string bitsize, string dispsize, string length,
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string format, dag operands>
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: Operand<!cast<ValueType>("i"##bitsize)> {
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let PrintMethod = "print"##format##"Operand";
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let EncoderMethod = "get"##format##dispsize##length##"Encoding";
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let DecoderMethod =
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"decode"##format##bitsize##"Disp"##dispsize##length##"Operand";
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let MIOperandInfo = operands;
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let ParserMatchClass =
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!cast<AddressAsmOperand>(format##bitsize##"Disp"##dispsize##length);
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}
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// Constructs both a DAG pattern and instruction operand for an addressing mode.
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// FORMAT, BITSIZE, DISPSIZE and LENGTH are the parameters to an associated
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// AddressAsmOperand. OPERANDS is a list of NUMOPS individual operands
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// (base register, displacement, etc.). SELTYPE is the type of the memory
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// operand for selection purposes; sometimes we want different selection
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// choices for the same underlying addressing mode. SUFFIX is similarly
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// a suffix appended to the displacement for selection purposes;
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// e.g. we want to reject small 20-bit displacements if a 12-bit form
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// also exists, but we want to accept them otherwise.
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class AddressingMode<string seltype, string bitsize, string dispsize,
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string suffix, string length, int numops, string format,
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dag operands>
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: ComplexPattern<!cast<ValueType>("i"##bitsize), numops,
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"select"##seltype##dispsize##suffix##length,
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[add, sub, or, frameindex, z_adjdynalloc]>,
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AddressOperand<bitsize, dispsize, length, format, operands>;
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// An addressing mode with a base and displacement but no index.
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class BDMode<string type, string bitsize, string dispsize, string suffix>
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: AddressingMode<type, bitsize, dispsize, suffix, "", 2, "BDAddr",
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(ops !cast<RegisterOperand>("ADDR"##bitsize),
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!cast<Operand>("disp"##dispsize##"imm"##bitsize))>;
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// An addressing mode with a base, displacement and index.
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class BDXMode<string type, string bitsize, string dispsize, string suffix>
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: AddressingMode<type, bitsize, dispsize, suffix, "", 3, "BDXAddr",
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(ops !cast<RegisterOperand>("ADDR"##bitsize),
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!cast<Operand>("disp"##dispsize##"imm"##bitsize),
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!cast<RegisterOperand>("ADDR"##bitsize))>;
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// A BDMode paired with an immediate length operand of LENSIZE bits.
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class BDLMode<string type, string bitsize, string dispsize, string suffix,
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string lensize>
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: AddressingMode<type, bitsize, dispsize, suffix, "Len"##lensize, 3,
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"BDLAddr",
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(ops !cast<RegisterOperand>("ADDR"##bitsize),
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!cast<Operand>("disp"##dispsize##"imm"##bitsize),
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!cast<Operand>("imm"##bitsize))>;
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// A BDMode paired with a register length operand.
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class BDRMode<string type, string bitsize, string dispsize, string suffix>
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: AddressingMode<type, bitsize, dispsize, suffix, "", 3, "BDRAddr",
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(ops !cast<RegisterOperand>("ADDR"##bitsize),
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!cast<Operand>("disp"##dispsize##"imm"##bitsize),
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!cast<RegisterOperand>("GR"##bitsize))>;
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// An addressing mode with a base, displacement and a vector index.
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class BDVMode<string bitsize, string dispsize>
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: AddressOperand<bitsize, dispsize, "", "BDVAddr",
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(ops !cast<RegisterOperand>("ADDR"##bitsize),
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!cast<Operand>("disp"##dispsize##"imm"##bitsize),
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!cast<RegisterOperand>("VR128"))>;
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//===----------------------------------------------------------------------===//
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// Extracting immediate operands from nodes
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// These all create MVT::i64 nodes to ensure the value is not sign-extended
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// when converted from an SDNode to a MachineOperand later on.
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//===----------------------------------------------------------------------===//
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// Bits 0-15 (counting from the lsb).
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def LL16 : SDNodeXForm<imm, [{
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uint64_t Value = N->getZExtValue() & 0x000000000000FFFFULL;
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return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);
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}]>;
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// Bits 16-31 (counting from the lsb).
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def LH16 : SDNodeXForm<imm, [{
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uint64_t Value = (N->getZExtValue() & 0x00000000FFFF0000ULL) >> 16;
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return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);
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}]>;
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// Bits 32-47 (counting from the lsb).
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def HL16 : SDNodeXForm<imm, [{
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uint64_t Value = (N->getZExtValue() & 0x0000FFFF00000000ULL) >> 32;
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return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);
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}]>;
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// Bits 48-63 (counting from the lsb).
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def HH16 : SDNodeXForm<imm, [{
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uint64_t Value = (N->getZExtValue() & 0xFFFF000000000000ULL) >> 48;
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return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);
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}]>;
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// Low 32 bits.
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def LF32 : SDNodeXForm<imm, [{
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uint64_t Value = N->getZExtValue() & 0x00000000FFFFFFFFULL;
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return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);
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}]>;
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// High 32 bits.
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def HF32 : SDNodeXForm<imm, [{
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uint64_t Value = N->getZExtValue() >> 32;
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return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);
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}]>;
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// Truncate an immediate to a 8-bit signed quantity.
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def SIMM8 : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(int8_t(N->getZExtValue()), SDLoc(N),
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MVT::i64);
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}]>;
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// Truncate an immediate to a 8-bit unsigned quantity.
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def UIMM8 : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(uint8_t(N->getZExtValue()), SDLoc(N),
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MVT::i64);
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}]>;
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// Truncate an immediate to a 8-bit unsigned quantity and mask off low bit.
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def UIMM8EVEN : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(N->getZExtValue() & 0xfe, SDLoc(N),
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MVT::i64);
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}]>;
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// Truncate an immediate to a 12-bit unsigned quantity.
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def UIMM12 : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(N->getZExtValue() & 0xfff, SDLoc(N),
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MVT::i64);
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}]>;
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// Truncate an immediate to a 16-bit signed quantity.
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def SIMM16 : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(int16_t(N->getZExtValue()), SDLoc(N),
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MVT::i64);
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}]>;
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// Negate and then truncate an immediate to a 16-bit signed quantity.
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def NEGSIMM16 : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(int16_t(-N->getZExtValue()), SDLoc(N),
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MVT::i64);
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}]>;
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// Truncate an immediate to a 16-bit unsigned quantity.
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def UIMM16 : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(uint16_t(N->getZExtValue()), SDLoc(N),
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MVT::i64);
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}]>;
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// Truncate an immediate to a 32-bit signed quantity.
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def SIMM32 : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(int32_t(N->getZExtValue()), SDLoc(N),
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MVT::i64);
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}]>;
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// Negate and then truncate an immediate to a 32-bit unsigned quantity.
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def NEGSIMM32 : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(int32_t(-N->getZExtValue()), SDLoc(N),
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MVT::i64);
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}]>;
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// Truncate an immediate to a 32-bit unsigned quantity.
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def UIMM32 : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(uint32_t(N->getZExtValue()), SDLoc(N),
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MVT::i64);
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}]>;
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// Negate and then truncate an immediate to a 32-bit unsigned quantity.
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def NEGUIMM32 : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(uint32_t(-N->getZExtValue()), SDLoc(N),
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MVT::i64);
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}]>;
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// Truncate an immediate to a 48-bit unsigned quantity.
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def UIMM48 : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(uint64_t(N->getZExtValue()) & 0xffffffffffff,
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SDLoc(N), MVT::i64);
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}]>;
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//===----------------------------------------------------------------------===//
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// Immediate asm operands.
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//===----------------------------------------------------------------------===//
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def U1Imm : ImmediateAsmOperand<"U1Imm">;
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def U2Imm : ImmediateAsmOperand<"U2Imm">;
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def U3Imm : ImmediateAsmOperand<"U3Imm">;
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def U4Imm : ImmediateAsmOperand<"U4Imm">;
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def U6Imm : ImmediateAsmOperand<"U6Imm">;
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def S8Imm : ImmediateAsmOperand<"S8Imm">;
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def U8Imm : ImmediateAsmOperand<"U8Imm">;
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def U12Imm : ImmediateAsmOperand<"U12Imm">;
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def S16Imm : ImmediateAsmOperand<"S16Imm">;
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def U16Imm : ImmediateAsmOperand<"U16Imm">;
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def S32Imm : ImmediateAsmOperand<"S32Imm">;
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def U32Imm : ImmediateAsmOperand<"U32Imm">;
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def U48Imm : ImmediateAsmOperand<"U48Imm">;
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//===----------------------------------------------------------------------===//
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// i32 immediates
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//===----------------------------------------------------------------------===//
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// Immediates for the lower and upper 16 bits of an i32, with the other
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// bits of the i32 being zero.
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def imm32ll16 : Immediate<i32, [{
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return SystemZ::isImmLL(N->getZExtValue());
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}], LL16, "U16Imm">;
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def imm32lh16 : Immediate<i32, [{
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return SystemZ::isImmLH(N->getZExtValue());
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}], LH16, "U16Imm">;
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// Immediates for the lower and upper 16 bits of an i32, with the other
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// bits of the i32 being one.
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def imm32ll16c : Immediate<i32, [{
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return SystemZ::isImmLL(uint32_t(~N->getZExtValue()));
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}], LL16, "U16Imm">;
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def imm32lh16c : Immediate<i32, [{
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return SystemZ::isImmLH(uint32_t(~N->getZExtValue()));
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}], LH16, "U16Imm">;
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// Short immediates
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def imm32zx1 : Immediate<i32, [{
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return isUInt<1>(N->getZExtValue());
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}], NOOP_SDNodeXForm, "U1Imm">;
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def imm32zx2 : Immediate<i32, [{
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return isUInt<2>(N->getZExtValue());
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}], NOOP_SDNodeXForm, "U2Imm">;
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def imm32zx3 : Immediate<i32, [{
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return isUInt<3>(N->getZExtValue());
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}], NOOP_SDNodeXForm, "U3Imm">;
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def imm32zx4 : Immediate<i32, [{
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return isUInt<4>(N->getZExtValue());
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}], NOOP_SDNodeXForm, "U4Imm">;
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// Note: this enforces an even value during code generation only.
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// When used from the assembler, any 4-bit value is allowed.
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def imm32zx4even : Immediate<i32, [{
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return isUInt<4>(N->getZExtValue());
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}], UIMM8EVEN, "U4Imm">;
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def imm32zx6 : Immediate<i32, [{
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return isUInt<6>(N->getZExtValue());
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}], NOOP_SDNodeXForm, "U6Imm">;
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def imm32sx8 : Immediate<i32, [{
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return isInt<8>(N->getSExtValue());
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}], SIMM8, "S8Imm">;
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def imm32zx8 : Immediate<i32, [{
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return isUInt<8>(N->getZExtValue());
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}], UIMM8, "U8Imm">;
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def imm32zx8trunc : Immediate<i32, [{}], UIMM8, "U8Imm">;
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def imm32zx12 : Immediate<i32, [{
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return isUInt<12>(N->getZExtValue());
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}], UIMM12, "U12Imm">;
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def imm32sx16 : Immediate<i32, [{
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return isInt<16>(N->getSExtValue());
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}], SIMM16, "S16Imm">;
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def imm32sx16n : Immediate<i32, [{
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return isInt<16>(-N->getSExtValue());
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}], NEGSIMM16, "S16Imm">;
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def imm32zx16 : Immediate<i32, [{
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return isUInt<16>(N->getZExtValue());
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}], UIMM16, "U16Imm">;
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def imm32sx16trunc : Immediate<i32, [{}], SIMM16, "S16Imm">;
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def imm32zx16trunc : Immediate<i32, [{}], UIMM16, "U16Imm">;
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// Full 32-bit immediates. we need both signed and unsigned versions
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// because the assembler is picky. E.g. AFI requires signed operands
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// while NILF requires unsigned ones.
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def simm32 : Immediate<i32, [{}], SIMM32, "S32Imm">;
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def uimm32 : Immediate<i32, [{}], UIMM32, "U32Imm">;
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def simm32n : Immediate<i32, [{
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return isInt<32>(-N->getSExtValue());
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}], NEGSIMM32, "S32Imm">;
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def imm32 : ImmLeaf<i32, [{}]>;
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//===----------------------------------------------------------------------===//
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// 64-bit immediates
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//===----------------------------------------------------------------------===//
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// Immediates for 16-bit chunks of an i64, with the other bits of the
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// i32 being zero.
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def imm64ll16 : Immediate<i64, [{
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return SystemZ::isImmLL(N->getZExtValue());
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}], LL16, "U16Imm">;
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def imm64lh16 : Immediate<i64, [{
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return SystemZ::isImmLH(N->getZExtValue());
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}], LH16, "U16Imm">;
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def imm64hl16 : Immediate<i64, [{
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return SystemZ::isImmHL(N->getZExtValue());
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}], HL16, "U16Imm">;
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def imm64hh16 : Immediate<i64, [{
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return SystemZ::isImmHH(N->getZExtValue());
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}], HH16, "U16Imm">;
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// Immediates for 16-bit chunks of an i64, with the other bits of the
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// i32 being one.
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def imm64ll16c : Immediate<i64, [{
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return SystemZ::isImmLL(uint64_t(~N->getZExtValue()));
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}], LL16, "U16Imm">;
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def imm64lh16c : Immediate<i64, [{
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return SystemZ::isImmLH(uint64_t(~N->getZExtValue()));
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}], LH16, "U16Imm">;
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def imm64hl16c : Immediate<i64, [{
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return SystemZ::isImmHL(uint64_t(~N->getZExtValue()));
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}], HL16, "U16Imm">;
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def imm64hh16c : Immediate<i64, [{
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return SystemZ::isImmHH(uint64_t(~N->getZExtValue()));
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}], HH16, "U16Imm">;
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// Immediates for the lower and upper 32 bits of an i64, with the other
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// bits of the i32 being zero.
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def imm64lf32 : Immediate<i64, [{
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return SystemZ::isImmLF(N->getZExtValue());
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|
}], LF32, "U32Imm">;
|
|
|
|
def imm64hf32 : Immediate<i64, [{
|
|
return SystemZ::isImmHF(N->getZExtValue());
|
|
}], HF32, "U32Imm">;
|
|
|
|
// Immediates for the lower and upper 32 bits of an i64, with the other
|
|
// bits of the i32 being one.
|
|
def imm64lf32c : Immediate<i64, [{
|
|
return SystemZ::isImmLF(uint64_t(~N->getZExtValue()));
|
|
}], LF32, "U32Imm">;
|
|
|
|
def imm64hf32c : Immediate<i64, [{
|
|
return SystemZ::isImmHF(uint64_t(~N->getZExtValue()));
|
|
}], HF32, "U32Imm">;
|
|
|
|
// Short immediates.
|
|
def imm64sx8 : Immediate<i64, [{
|
|
return isInt<8>(N->getSExtValue());
|
|
}], SIMM8, "S8Imm">;
|
|
|
|
def imm64zx8 : Immediate<i64, [{
|
|
return isUInt<8>(N->getSExtValue());
|
|
}], UIMM8, "U8Imm">;
|
|
|
|
def imm64sx16 : Immediate<i64, [{
|
|
return isInt<16>(N->getSExtValue());
|
|
}], SIMM16, "S16Imm">;
|
|
|
|
def imm64sx16n : Immediate<i64, [{
|
|
return isInt<16>(-N->getSExtValue());
|
|
}], NEGSIMM16, "S16Imm">;
|
|
|
|
def imm64zx16 : Immediate<i64, [{
|
|
return isUInt<16>(N->getZExtValue());
|
|
}], UIMM16, "U16Imm">;
|
|
|
|
def imm64sx32 : Immediate<i64, [{
|
|
return isInt<32>(N->getSExtValue());
|
|
}], SIMM32, "S32Imm">;
|
|
|
|
def imm64sx32n : Immediate<i64, [{
|
|
return isInt<32>(-N->getSExtValue());
|
|
}], NEGSIMM32, "S32Imm">;
|
|
|
|
def imm64zx32 : Immediate<i64, [{
|
|
return isUInt<32>(N->getZExtValue());
|
|
}], UIMM32, "U32Imm">;
|
|
|
|
def imm64zx32n : Immediate<i64, [{
|
|
return isUInt<32>(-N->getSExtValue());
|
|
}], NEGUIMM32, "U32Imm">;
|
|
|
|
def imm64zx48 : Immediate<i64, [{
|
|
return isUInt<64>(N->getZExtValue());
|
|
}], UIMM48, "U48Imm">;
|
|
|
|
def imm64 : ImmLeaf<i64, [{}]>, Operand<i64>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Floating-point immediates
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Floating-point zero.
|
|
def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>;
|
|
|
|
// Floating point negative zero.
|
|
def fpimmneg0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(-0.0); }]>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Symbolic address operands
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// PC-relative asm operands.
|
|
def PCRel12 : PCRelAsmOperand<"12">;
|
|
def PCRel16 : PCRelAsmOperand<"16">;
|
|
def PCRel24 : PCRelAsmOperand<"24">;
|
|
def PCRel32 : PCRelAsmOperand<"32">;
|
|
def PCRelTLS16 : PCRelTLSAsmOperand<"16">;
|
|
def PCRelTLS32 : PCRelTLSAsmOperand<"32">;
|
|
|
|
// PC-relative offsets of a basic block. The offset is sign-extended
|
|
// and multiplied by 2.
|
|
def brtarget16 : PCRelOperand<OtherVT, PCRel16> {
|
|
let EncoderMethod = "getPC16DBLEncoding";
|
|
let DecoderMethod = "decodePC16DBLBranchOperand";
|
|
}
|
|
def brtarget32 : PCRelOperand<OtherVT, PCRel32> {
|
|
let EncoderMethod = "getPC32DBLEncoding";
|
|
let DecoderMethod = "decodePC32DBLBranchOperand";
|
|
}
|
|
|
|
// Variants of brtarget for use with branch prediction preload.
|
|
def brtarget12bpp : PCRelOperand<OtherVT, PCRel12> {
|
|
let EncoderMethod = "getPC12DBLBPPEncoding";
|
|
let DecoderMethod = "decodePC12DBLBranchOperand";
|
|
}
|
|
def brtarget16bpp : PCRelOperand<OtherVT, PCRel16> {
|
|
let EncoderMethod = "getPC16DBLBPPEncoding";
|
|
let DecoderMethod = "decodePC16DBLBranchOperand";
|
|
}
|
|
def brtarget24bpp : PCRelOperand<OtherVT, PCRel24> {
|
|
let EncoderMethod = "getPC24DBLBPPEncoding";
|
|
let DecoderMethod = "decodePC24DBLBranchOperand";
|
|
}
|
|
|
|
// Variants of brtarget16/32 with an optional additional TLS symbol.
|
|
// These are used to annotate calls to __tls_get_offset.
|
|
def tlssym : Operand<i64> { }
|
|
def brtarget16tls : PCRelTLSOperand<OtherVT, PCRelTLS16> {
|
|
let MIOperandInfo = (ops brtarget16:$func, tlssym:$sym);
|
|
let EncoderMethod = "getPC16DBLTLSEncoding";
|
|
let DecoderMethod = "decodePC16DBLBranchOperand";
|
|
}
|
|
def brtarget32tls : PCRelTLSOperand<OtherVT, PCRelTLS32> {
|
|
let MIOperandInfo = (ops brtarget32:$func, tlssym:$sym);
|
|
let EncoderMethod = "getPC32DBLTLSEncoding";
|
|
let DecoderMethod = "decodePC32DBLBranchOperand";
|
|
}
|
|
|
|
// A PC-relative offset of a global value. The offset is sign-extended
|
|
// and multiplied by 2.
|
|
def pcrel32 : PCRelAddress<i64, "pcrel32", PCRel32> {
|
|
let EncoderMethod = "getPC32DBLEncoding";
|
|
let DecoderMethod = "decodePC32DBLOperand";
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Addressing modes
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// 12-bit displacement operands.
|
|
def disp12imm32 : Operand<i32>;
|
|
def disp12imm64 : Operand<i64>;
|
|
|
|
// 20-bit displacement operands.
|
|
def disp20imm32 : Operand<i32>;
|
|
def disp20imm64 : Operand<i64>;
|
|
|
|
def BDAddr32Disp12 : AddressAsmOperand<"BDAddr", "32", "12">;
|
|
def BDAddr32Disp20 : AddressAsmOperand<"BDAddr", "32", "20">;
|
|
def BDAddr64Disp12 : AddressAsmOperand<"BDAddr", "64", "12">;
|
|
def BDAddr64Disp20 : AddressAsmOperand<"BDAddr", "64", "20">;
|
|
def BDXAddr64Disp12 : AddressAsmOperand<"BDXAddr", "64", "12">;
|
|
def BDXAddr64Disp20 : AddressAsmOperand<"BDXAddr", "64", "20">;
|
|
def BDLAddr64Disp12Len4 : AddressAsmOperand<"BDLAddr", "64", "12", "Len4">;
|
|
def BDLAddr64Disp12Len8 : AddressAsmOperand<"BDLAddr", "64", "12", "Len8">;
|
|
def BDRAddr64Disp12 : AddressAsmOperand<"BDRAddr", "64", "12">;
|
|
def BDVAddr64Disp12 : AddressAsmOperand<"BDVAddr", "64", "12">;
|
|
|
|
// DAG patterns and operands for addressing modes. Each mode has
|
|
// the form <type><range><group>[<len>] where:
|
|
//
|
|
// <type> is one of:
|
|
// shift : base + displacement (32-bit)
|
|
// bdaddr : base + displacement
|
|
// mviaddr : like bdaddr, but reject cases with a natural index
|
|
// bdxaddr : base + displacement + index
|
|
// laaddr : like bdxaddr, but used for Load Address operations
|
|
// dynalloc : base + displacement + index + ADJDYNALLOC
|
|
// bdladdr : base + displacement with a length field
|
|
// bdvaddr : base + displacement with a vector index
|
|
//
|
|
// <range> is one of:
|
|
// 12 : the displacement is an unsigned 12-bit value
|
|
// 20 : the displacement is a signed 20-bit value
|
|
//
|
|
// <group> is one of:
|
|
// pair : used when there is an equivalent instruction with the opposite
|
|
// range value (12 or 20)
|
|
// only : used when there is no equivalent instruction with the opposite
|
|
// range value
|
|
//
|
|
// <len> is one of:
|
|
//
|
|
// <empty> : there is no length field
|
|
// len8 : the length field is 8 bits, with a range of [1, 0x100].
|
|
def shift12only : BDMode <"BDAddr", "32", "12", "Only">;
|
|
def shift20only : BDMode <"BDAddr", "32", "20", "Only">;
|
|
def bdaddr12only : BDMode <"BDAddr", "64", "12", "Only">;
|
|
def bdaddr12pair : BDMode <"BDAddr", "64", "12", "Pair">;
|
|
def bdaddr20only : BDMode <"BDAddr", "64", "20", "Only">;
|
|
def bdaddr20pair : BDMode <"BDAddr", "64", "20", "Pair">;
|
|
def mviaddr12pair : BDMode <"MVIAddr", "64", "12", "Pair">;
|
|
def mviaddr20pair : BDMode <"MVIAddr", "64", "20", "Pair">;
|
|
def bdxaddr12only : BDXMode<"BDXAddr", "64", "12", "Only">;
|
|
def bdxaddr12pair : BDXMode<"BDXAddr", "64", "12", "Pair">;
|
|
def bdxaddr20only : BDXMode<"BDXAddr", "64", "20", "Only">;
|
|
def bdxaddr20only128 : BDXMode<"BDXAddr", "64", "20", "Only128">;
|
|
def bdxaddr20pair : BDXMode<"BDXAddr", "64", "20", "Pair">;
|
|
def dynalloc12only : BDXMode<"DynAlloc", "64", "12", "Only">;
|
|
def laaddr12pair : BDXMode<"LAAddr", "64", "12", "Pair">;
|
|
def laaddr20pair : BDXMode<"LAAddr", "64", "20", "Pair">;
|
|
def bdladdr12onlylen4 : BDLMode<"BDLAddr", "64", "12", "Only", "4">;
|
|
def bdladdr12onlylen8 : BDLMode<"BDLAddr", "64", "12", "Only", "8">;
|
|
def bdraddr12only : BDRMode<"BDRAddr", "64", "12", "Only">;
|
|
def bdvaddr12only : BDVMode< "64", "12">;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Miscellaneous
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// A 4-bit condition-code mask.
|
|
def cond4 : PatLeaf<(i32 imm), [{ return (N->getZExtValue() < 16); }]>,
|
|
Operand<i32> {
|
|
let PrintMethod = "printCond4Operand";
|
|
}
|