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4893e095df
This patch teaches llvm-mca how to identify register writes that implicitly zero the upper portion of a super-register. On X86-64, a general purpose register is implemented in hardware as a 64-bit register. Quoting the Intel 64 Software Developer's Manual: "an update to the lower 32 bits of a 64 bit integer register is architecturally defined to zero extend the upper 32 bits". Also, a write to an XMM register performed by an AVX instruction implicitly zeroes the upper 128 bits of the aliasing YMM register. This patch adds a new method named clearsSuperRegisters to the MCInstrAnalysis interface to help identify instructions that implicitly clear the upper portion of a super-register. The rest of the patch teaches llvm-mca how to use that new method to obtain the information, and update the register dependencies accordingly. I compared the kernels from tests clear-super-register-1.s and clear-super-register-2.s against the output from perf on btver2. Previously there was a large discrepancy between the estimated IPC and the measured IPC. Now the differences are mostly in the noise. Differential Revision: https://reviews.llvm.org/D48225 llvm-svn: 335113
37 lines
1.1 KiB
C++
37 lines
1.1 KiB
C++
//===- MCInstrAnalysis.cpp - InstrDesc target hooks -----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/MC/MCInstrAnalysis.h"
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#include "llvm/ADT/APInt.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include <cstdint>
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using namespace llvm;
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bool MCInstrAnalysis::clearsSuperRegisters(const MCRegisterInfo &MRI,
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const MCInst &Inst,
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APInt &Writes) const {
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Writes.clearAllBits();
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return false;
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}
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bool MCInstrAnalysis::evaluateBranch(const MCInst &Inst, uint64_t Addr,
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uint64_t Size, uint64_t &Target) const {
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if (Inst.getNumOperands() == 0 ||
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Info->get(Inst.getOpcode()).OpInfo[0].OperandType != MCOI::OPERAND_PCREL)
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return false;
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int64_t Imm = Inst.getOperand(0).getImm();
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Target = Addr+Size+Imm;
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return true;
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}
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