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262321d1ff
This patch lets the llvm tools handle the new HVX target features that
are added by frontend (clang). The target-features are of the form
"hvx-length64b" for 64 Byte HVX mode, "hvx-length128b" for 128 Byte mode HVX.
"hvx-double" is an alias to "hvx-length128b" and is soon will be deprecated.
The hvx version target feature is upgated form "+hvx" to "+hvxv{version_number}.
Eg: "+hvxv62"
For the correct HVX code generation, the user must use the following
target features.
For 64B mode: "+hvxv62" "+hvx-length64b"
For 128B mode: "+hvxv62" "+hvx-length128b"
Clang picks a default length if none is specified. If for some reason,
no hvx-length is specified to llvm, the compilation will bail out.
There is a corresponding clang patch.
Differential Revision: https://reviews.llvm.org/D38851
llvm-svn: 316101
53 lines
2.5 KiB
LLVM
53 lines
2.5 KiB
LLVM
; RUN: llc -march=hexagon < %s | FileCheck %s
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; CHECK: = vmem(r{{[0-9]+}}++#1)
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target triple = "hexagon-unknown--elf"
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declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #0
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declare <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32>, <32 x i32>) #0
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declare <64 x i32> @llvm.hexagon.V6.vzb.128B(<32 x i32>) #0
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declare <32 x i32> @llvm.hexagon.V6.vsathub.128B(<32 x i32>, <32 x i32>) #0
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declare <64 x i32> @llvm.hexagon.V6.vaddh.dv.128B(<64 x i32>, <64 x i32>) #0
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declare <64 x i32> @llvm.hexagon.V6.vadduhsat.dv.128B(<64 x i32>, <64 x i32>) #0
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declare <32 x i32> @llvm.hexagon.V6.vabsdiffuh.128B(<32 x i32>, <32 x i32>) #0
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define void @fred() #1 {
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entry:
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br i1 undef, label %b1, label %call_destructor.exit
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b1: ; preds = %entry
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br label %b2
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b2: ; preds = %b1, %b2
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%c2.host32.sroa.3.0 = phi <128 x i8> [ %5, %b2 ], [ undef, %b1 ]
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%sobel_halide.s0.x.x = phi i32 [ %17, %b2 ], [ 0, %b1 ]
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%0 = add nsw i32 %sobel_halide.s0.x.x, undef
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%1 = shl i32 %0, 7
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%2 = add nsw i32 %1, 128
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%3 = getelementptr inbounds i8, i8* undef, i32 %2
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%4 = bitcast i8* %3 to <128 x i8>*
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%5 = load <128 x i8>, <128 x i8>* %4, align 128
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%6 = bitcast <128 x i8> %c2.host32.sroa.3.0 to <32 x i32>
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%7 = tail call <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32> undef, <32 x i32> %6, i32 1)
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%8 = tail call <64 x i32> @llvm.hexagon.V6.vzb.128B(<32 x i32> %7) #1
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%9 = tail call <64 x i32> @llvm.hexagon.V6.vadduhsat.dv.128B(<64 x i32> undef, <64 x i32> %8) #1
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%10 = tail call <64 x i32> @llvm.hexagon.V6.vadduhsat.dv.128B(<64 x i32> %9, <64 x i32> undef) #1
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%11 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %10)
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%12 = tail call <32 x i32> @llvm.hexagon.V6.vabsdiffuh.128B(<32 x i32> undef, <32 x i32> %11) #1
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%13 = tail call <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32> %12, <32 x i32> undef)
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%14 = tail call <64 x i32> @llvm.hexagon.V6.vaddh.dv.128B(<64 x i32> undef, <64 x i32> %13) #1
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%15 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %14) #1
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%16 = tail call <32 x i32> @llvm.hexagon.V6.vsathub.128B(<32 x i32> %15, <32 x i32> undef) #1
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store <32 x i32> %16, <32 x i32>* undef, align 128
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%17 = add nuw nsw i32 %sobel_halide.s0.x.x, 1
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br label %b2
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call_destructor.exit: ; preds = %entry
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ret void
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}
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declare <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32>, <32 x i32>, i32) #0
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }
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