Simon Pilgrim ae3b946d06 [SchedModel] Complete models shouldn't match against itineraries when they don't use them (PR35639) ...

For schedule models that don't use itineraries, checkCompleteness still checks that an instruction has a matching itinerary instead of skipping and going straight to matching the InstRWs. That doesn't seem to match what happens in TargetSchedule.cpp

This patch causes problems for a number of models that had been incorrectly flagged as complete.

Differential Revision: https://reviews.llvm.org/D43235

llvm-svn: 329280

2018-04-05 13:11:36 +00:00

..

AsmMatcherEmitter.cpp

Fix signed/unsigned comparison warning in AsmGenMatcher generated code. NFCI.

2018-02-17 12:29:47 +00:00

AsmWriterEmitter.cpp

[AArch64][TableGen] Skip tied result operands for InstAlias

2017-11-20 14:36:40 +00:00

AsmWriterInst.cpp

[TableGen] Remove the CGIOpNo from AsmWriterOperand as its not used for anything. NFC

2016-01-22 05:59:37 +00:00

AsmWriterInst.h

[TableGen] Reorder fields in AsmWriterOperand to remove padding and reduce size. NFC

2016-01-22 05:59:40 +00:00

Attributes.cpp

Remove redundant includes from utils/TableGen.

2017-12-13 21:31:13 +00:00

CallingConvEmitter.cpp

[TableGen] Simplify CallingConvEmitter.cpp. NFC.

2017-10-16 14:52:26 +00:00

CMakeLists.txt

TableGen: Allow setting SDNodeProperties on intrinsics

2017-12-20 19:36:28 +00:00

CodeEmitterGen.cpp

[tablegen] Avoid creating a temporary vector in getInstructionCase

2017-07-04 06:16:53 +00:00

CodeGenDAGPatterns.cpp

Fix a bunch of typoes. NFC

2018-03-30 22:22:31 +00:00

CodeGenDAGPatterns.h

[TableGen] Print more helpful information in case of type contradiction

2017-12-21 17:12:43 +00:00

CodeGenHwModes.cpp

TableGen support for parameterized register class information

2017-09-14 16:56:21 +00:00

CodeGenHwModes.h

TableGen support for parameterized register class information

2017-09-14 16:56:21 +00:00

CodeGenInstruction.cpp

[globalisel][tablegen] Generalize pointer-type inference by introducing ptypeN. NFC

2017-11-18 00:16:44 +00:00

CodeGenInstruction.h

Fix layering of MachineValueType.h by moving it from CodeGen to Support

2018-03-23 23:58:25 +00:00

CodeGenIntrinsics.h

Fix layering of MachineValueType.h by moving it from CodeGen to Support

2018-03-23 23:58:25 +00:00

CodeGenMapTable.cpp

[mips] Improve diagnostics for instruction mapping

2018-01-08 16:25:40 +00:00

CodeGenRegisters.cpp

[X86] Add phony registers for high halves of regs with low halves

2018-03-20 18:46:55 +00:00

CodeGenRegisters.h

Fix layering of MachineValueType.h by moving it from CodeGen to Support

2018-03-23 23:58:25 +00:00

CodeGenSchedule.cpp

[SchedModel] Complete models shouldn't match against itineraries when they don't use them (PR35639)

2018-04-05 13:11:36 +00:00

CodeGenSchedule.h

[MC][Tablegen] Allow the definition of processor register files in the scheduling model for llvm-mca

2018-04-03 13:36:24 +00:00

CodeGenTarget.cpp

TableGen: More helpful error messages

2018-04-01 17:08:49 +00:00

CodeGenTarget.h

[MachineOperand][Target] MachineOperand::isRenamable semantics changes

2018-02-23 18:25:08 +00:00

CTagsEmitter.cpp

Revert r318822 "[llvm-tblgen] - Stop using std::string in RecordKeeper."

2017-11-23 06:52:44 +00:00

DAGISelEmitter.cpp

Allow separation of declarations and definitions in <Target>ISelDAGToDAG.inc

2017-11-10 18:36:04 +00:00

DAGISelMatcher.cpp

Remove redundant includes from utils/TableGen.

2017-12-13 21:31:13 +00:00

DAGISelMatcher.h

Fix layering of MachineValueType.h by moving it from CodeGen to Support

2018-03-23 23:58:25 +00:00

DAGISelMatcherEmitter.cpp

[SelectionDAG] Add a isel matcher op to check the type of node results other than result 0.

2017-11-22 07:11:01 +00:00

DAGISelMatcherGen.cpp

TableGen support for parameterized register class information

2017-09-14 16:56:21 +00:00

DAGISelMatcherOpt.cpp

[TableGen] Use less stack in DAGISelMatcherOpt

2017-02-06 19:41:44 +00:00

DFAPacketizerEmitter.cpp

Avoid int to string conversion in Twine or raw_ostream contexts.

2017-12-28 16:58:54 +00:00

DisassemblerEmitter.cpp

Fix layering by moving X86DisassemblerDecoderCommon to Support

2018-03-23 23:58:20 +00:00

FastISelEmitter.cpp

Strip trailing whitespace

2017-10-06 15:33:55 +00:00

FixedLenDecoderEmitter.cpp

TableGen: Use DefInit::getDef() instead of the type's getRecord()

2018-03-05 14:01:30 +00:00

GlobalISelEmitter.cpp

Fix layering of MachineValueType.h by moving it from CodeGen to Support

2018-03-23 23:58:25 +00:00

InfoByHwMode.cpp

Remove redundant includes from utils/TableGen.

2017-12-13 21:31:13 +00:00

InfoByHwMode.h

Fix layering of MachineValueType.h by moving it from CodeGen to Support

2018-03-23 23:58:25 +00:00

InstrDocsEmitter.cpp

[Docs] Add tablegen backend for target opcode documentation

2017-11-14 15:35:15 +00:00

InstrInfoEmitter.cpp

[MachineOperand][Target] MachineOperand::isRenamable semantics changes

2018-02-23 18:25:08 +00:00

IntrinsicEmitter.cpp

Avoid int to string conversion in Twine or raw_ostream contexts.

2017-12-28 16:58:54 +00:00

LLVMBuild.txt

Add missing dependency (headers are included from MC, so a link dependency could exist easily enough)

2018-03-29 00:29:43 +00:00

OptParserEmitter.cpp

[Bash-autocompletion] Add support for -std=

2017-08-29 02:01:56 +00:00

PseudoLoweringEmitter.cpp

TableGen: Use StringInit instead of std::string for DagInit arg names

2016-12-05 06:00:46 +00:00

RegisterBankEmitter.cpp

[globalisel][regbank] Warn about MIR ambiguities when register bank/class names clash.

2017-11-01 22:13:05 +00:00

RegisterInfoEmitter.cpp

Fix layering of MachineValueType.h by moving it from CodeGen to Support

2018-03-23 23:58:25 +00:00

SDNodeProperties.cpp

TableGen: Allow setting SDNodeProperties on intrinsics

2017-12-20 19:36:28 +00:00

SDNodeProperties.h

TableGen: Allow setting SDNodeProperties on intrinsics

2017-12-20 19:36:28 +00:00

SearchableTableEmitter.cpp

TableGen: Support Intrinsic values in SearchableTable

2018-04-01 17:08:58 +00:00

SequenceToOffsetTable.h

Remove usages of deprecated std::unary_function and std::binary_function.

2017-09-14 18:33:25 +00:00

SubtargetEmitter.cpp

[Tablegen] Slightly refactor method SubtargetEmitter::EmitExtraProcessorInfo.

2018-04-04 11:53:13 +00:00

SubtargetFeatureInfo.cpp

Reverting r315590; it did not include changes for llvm-tblgen, which is causing link errors for several people.

2017-10-15 14:32:27 +00:00

SubtargetFeatureInfo.h

[globalisel][tablegen] Compute available feature bits correctly.

2017-04-29 17:30:09 +00:00

TableGen.cpp

Remove redundant includes from utils/TableGen.

2017-12-13 21:31:13 +00:00

TableGenBackends.h

[Docs] Add tablegen backend for target opcode documentation

2017-11-14 15:35:15 +00:00

tdtags

…

Types.cpp

[globalisel][tablegen] Import SelectionDAG's rule predicates and support the equivalent in GIRule.

2017-04-21 15:59:56 +00:00

Types.h

Check that emitted instructions meet their predicates on all targets except ARM, Mips, and X86.

2016-11-19 13:05:44 +00:00

X86DisassemblerShared.h

[X86] Use unique_ptr to simplify memory management. NFC

2018-03-24 07:15:47 +00:00

X86DisassemblerTables.cpp

[X86] Add a new disassembler opcode map for 3DNow. Stop treating 3DNow as an attribute.

2018-03-24 07:48:54 +00:00

X86DisassemblerTables.h

[X86] Add a new disassembler opcode map for 3DNow. Stop treating 3DNow as an attribute.

2018-03-24 07:48:54 +00:00

X86EVEX2VEXTablesEmitter.cpp

[X86] Rename VROUNDYPS* and VROUNDYPD* instructions to VROUNDPSY* and VROUNDPDY*. Fix itinerary mistake on all memory forms of VROUNDPD

2018-03-22 21:55:20 +00:00

X86FoldTablesEmitter.cpp

Fix a bunch of typoes. NFC

2018-03-30 22:22:31 +00:00

X86ModRMFilters.cpp

Second attempt at Removing special form of AddRegFrm used by FP instructions. These instructions can be handled by MRMXr instead.

2014-01-01 14:22:37 +00:00

X86ModRMFilters.h

fix trivial typos in comments; NFC

2017-07-04 13:09:29 +00:00

X86RecognizableInstr.cpp

[X86][TableGen] Add a missing error check to make sure EVEX instructions use one PS/PD/XS/XD prefixes.

2018-04-03 06:37:01 +00:00

X86RecognizableInstr.h

[X86] Reduce number of OpPrefix bits in TSFlags to 2. NFCI

2018-04-03 06:37:04 +00:00