mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-23 03:02:36 +01:00
f56c09c87f
If a resource can be held for multiple cycles in the schedule model then an instruction can be placed into the available queue, another instruction can be scheduled, but the first will not be taken back out if the two instructions hazard. To fix this make sure that we update the available queue even on the first MOp of a cycle, pushing available instructions back into the pending queue if they now conflict. This happens with some downstream schedules we have around MVE instruction scheduling where we use ResourceCycles=[2] to show the instruction executing over two beats. Apparently the test changes here are OK too. Differential Revision: https://reviews.llvm.org/D76909
372 lines
18 KiB
LLVM
372 lines
18 KiB
LLVM
; RUN: llc -O2 -mtriple powerpc-ibm-aix-xcoff -stop-after=machine-cp -verify-machineinstrs < %s | \
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; RUN: FileCheck --check-prefixes=CHECK,32BIT %s
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; RUN: llc -O2 -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \
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; RUN: -mtriple powerpc-ibm-aix-xcoff < %s | \
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; RUN: FileCheck --check-prefixes=CHECKASM,ASM32 %s
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define i32 @int_va_arg(i32 %a, ...) local_unnamed_addr {
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entry:
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%arg1 = alloca i8*, align 4
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%arg2 = alloca i8*, align 4
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%0 = bitcast i8** %arg1 to i8*
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call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %0)
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%1 = bitcast i8** %arg2 to i8*
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call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %1)
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call void @llvm.va_start(i8* nonnull %0)
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call void @llvm.va_copy(i8* nonnull %1, i8* nonnull %0)
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%argp.cur = load i8*, i8** %arg1, align 4
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%argp.next = getelementptr inbounds i8, i8* %argp.cur, i32 4
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store i8* %argp.next, i8** %arg1, align 4
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%2 = bitcast i8* %argp.cur to i32*
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%3 = load i32, i32* %2, align 4
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%add = add nsw i32 %3, %a
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%argp.cur2 = load i8*, i8** %arg2, align 4
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%argp.next3 = getelementptr inbounds i8, i8* %argp.cur2, i32 4
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store i8* %argp.next3, i8** %arg2, align 4
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%4 = bitcast i8* %argp.cur2 to i32*
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%5 = load i32, i32* %4, align 4
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%mul = shl i32 %5, 1
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%add4 = add nsw i32 %add, %mul
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call void @llvm.va_end(i8* nonnull %0)
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call void @llvm.va_end(i8* nonnull %1)
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call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %1)
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call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %0)
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ret i32 %add4
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}
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declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture)
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declare void @llvm.va_start(i8*)
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declare void @llvm.va_copy(i8*, i8*)
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declare void @llvm.va_end(i8*)
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declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture)
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; 32BIT-LABEL: name: int_va_arg
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; 32BIT-LABEL; liveins:
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; 32BIT-DAG: - { reg: '$r3', virtual-reg: '' }
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; 32BIT-DAG: - { reg: '$r4', virtual-reg: '' }
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; 32BIT-DAG: - { reg: '$r5', virtual-reg: '' }
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; 32BIT-DAG: - { reg: '$r6', virtual-reg: '' }
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; 32BIT-DAG: - { reg: '$r7', virtual-reg: '' }
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; 32BIT-DAG: - { reg: '$r8', virtual-reg: '' }
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; 32BIT-DAG: - { reg: '$r9', virtual-reg: '' }
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; 32BIT-DAG: - { reg: '$r10', virtual-reg: '' }
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; 32BIT-LABEL: fixedStack:
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; 32BIT-DAG: - { id: 0, type: default, offset: 28, size: 4
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; 32BIT-LABEL: stack:
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; 32BIT-DAG: - { id: 0, name: arg1, type: default, offset: 0, size: 4
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; 32BIT-DAG: - { id: 1, name: arg2, type: default, offset: 0, size: 4
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; 32BIT-LABEL: body: |
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; 32BIT-DAG: liveins: $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10
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; 32BIT-DAG: STW killed renamable $r4, 0, %fixed-stack.0 :: (store 4 into %fixed-stack.0)
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; 32BIT-DAG: STW killed renamable $r5, 4, %fixed-stack.0 :: (store 4 into %fixed-stack.0 + 4)
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; 32BIT-DAG: STW killed renamable $r6, 8, %fixed-stack.0 :: (store 4)
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; 32BIT-DAG: STW killed renamable $r7, 12, %fixed-stack.0 :: (store 4)
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; 32BIT-DAG: STW killed renamable $r8, 16, %fixed-stack.0 :: (store 4)
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; 32BIT-DAG: STW killed renamable $r9, 20, %fixed-stack.0 :: (store 4)
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; 32BIT-DAG: STW killed renamable $r10, 24, %fixed-stack.0 :: (store 4)
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; 32BIT-DAG: STW killed renamable $r4, 0, %stack.1.arg2 :: (store 4 into %ir.arg2)
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; 32BIT-DAG: renamable $r4 = ADDI %fixed-stack.0, 4
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; 32BIT-DAG: STW killed renamable $r11, 0, %stack.1.arg2 :: (store 4 into %ir.1)
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; 32BIT-DAG: renamable $r11 = ADDI %fixed-stack.0, 0
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; 32BIT-DAG: STW renamable $r11, 0, %stack.0.arg1 :: (store 4 into %ir.0)
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; 32BIT-DAG: STW renamable $r4, 0, %stack.0.arg1 :: (store 4 into %ir.arg1)
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; 32BIT-DAG: renamable $r5 = LWZ 0, %fixed-stack.0 :: (load 4 from %ir.2)
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; 32BIT-DAG: renamable $r4 = LWZ 0, %fixed-stack.0 :: (load 4 from %ir.4)
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; 32BIT-DAG: renamable $r3 = nsw ADD4 killed renamable $r5, killed renamable $r3
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; 32BIT-DAG: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r4
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; 32BIT-DAG: BLR implicit $lr, implicit $rm, implicit $r3
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; ASM32-LABEL: .int_va_arg:
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; set up fixed stack frame for incoming va_args r4->r10
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; ASM32-DAG: stw 4, 28(1)
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; ASM32-DAG: stw 5, 32(1)
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; ASM32-DAG: stw 6, 36(1)
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; ASM32-DAG: stw 7, 40(1)
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; ASM32-DAG: stw 8, 44(1)
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; ASM32-DAG: stw 9, 48(1)
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; ASM32-DAG: stw 10, 52(1)
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; load of arg1 from fixed stack offset
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; ASM32-DAG: lwz [[ARG1:[0-9]+]], 28(1)
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; va_copy load of arg2 from fixed stack offset
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; ASM32-DAG: lwz [[ARG2:[0-9]+]], 28(1)
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; ASM32-DAG: blr
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define i32 @int_stack_va_arg(i32 %one, i32 %two, i32 %three, i32 %four, i32 %five, i32 %six, i32 %seven, i32 %eight, ...) local_unnamed_addr {
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entry:
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%arg1 = alloca i8*, align 4
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%arg2 = alloca i8*, align 4
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%0 = bitcast i8** %arg1 to i8*
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call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %0)
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%1 = bitcast i8** %arg2 to i8*
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call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %1)
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call void @llvm.va_start(i8* nonnull %0)
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call void @llvm.va_copy(i8* nonnull %1, i8* nonnull %0)
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%add = add nsw i32 %two, %one
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%add2 = add nsw i32 %add, %three
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%add3 = add nsw i32 %add2, %four
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%add4 = add nsw i32 %add3, %five
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%add5 = add nsw i32 %add4, %six
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%add6 = add nsw i32 %add5, %seven
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%add7 = add nsw i32 %add6, %eight
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%argp.cur = load i8*, i8** %arg1, align 4
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%argp.next = getelementptr inbounds i8, i8* %argp.cur, i32 4
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store i8* %argp.next, i8** %arg1, align 4
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%2 = bitcast i8* %argp.cur to i32*
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%3 = load i32, i32* %2, align 4
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%add8 = add nsw i32 %add7, %3
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%argp.cur9 = load i8*, i8** %arg2, align 4
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%argp.next10 = getelementptr inbounds i8, i8* %argp.cur9, i32 4
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store i8* %argp.next10, i8** %arg2, align 4
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%4 = bitcast i8* %argp.cur9 to i32*
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%5 = load i32, i32* %4, align 4
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%mul = shl i32 %5, 1
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%add11 = add nsw i32 %add8, %mul
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call void @llvm.va_end(i8* nonnull %0)
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call void @llvm.va_end(i8* nonnull %1)
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call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %1)
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call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %0)
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ret i32 %add11
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}
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; 32BIT-LABEL: name: int_stack_va_arg
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; 32BIT-LABEL: liveins:
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; 32BIT-DAG: - { reg: '$r3', virtual-reg: '' }
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; 32BIT-DAG: - { reg: '$r4', virtual-reg: '' }
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; 32BIT-DAG: - { reg: '$r5', virtual-reg: '' }
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; 32BIT-DAG: - { reg: '$r6', virtual-reg: '' }
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; 32BIT-DAG: - { reg: '$r7', virtual-reg: '' }
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; 32BIT-DAG: - { reg: '$r8', virtual-reg: '' }
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; 32BIT-DAG: - { reg: '$r9', virtual-reg: '' }
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; 32BIT-DAG: - { reg: '$r10', virtual-reg: '' }
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; 32BIT-LABEL: fixedStack:
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; 32BIT-DAG: - { id: 0, type: default, offset: 56, size: 4
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; 32BIT-LABEL: stack:
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; 32BIT-DAG: - { id: 0, name: arg1, type: default, offset: 0, size: 4
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; 32BIT-DAG: - { id: 1, name: arg2, type: default, offset: 0, size: 4
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; 32BIT-LABEL: body: |
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; 32BIT-DAG: liveins: $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10
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; 32BIT-DAG: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r4
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; 32BIT-DAG: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r5
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; 32BIT-DAG: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r6
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; 32BIT-DAG: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r7
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; 32BIT-DAG: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r8
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; 32BIT-DAG: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r9
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; 32BIT-DAG: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r10
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; 32BIT-DAG: renamable $r3 = nsw ADD4 killed renamable $r4, killed renamable $r3
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; 32BIT-DAG: renamable $r4 = ADDI %fixed-stack.0, 0
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; 32BIT-DAG: STW killed renamable $r4, 0, %stack.0.arg1 :: (store 4 into %ir.arg1)
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; 32BIT-DAG: renamable $r3 = nsw ADD4 killed renamable $r3, renamable $r4
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; 32BIT-DAG: renamable $r4 = LWZ 0, %fixed-stack.0 :: (load 4 from %ir.4, align 8)
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; 32BIT-DAG: renamable $r11 = LI 4
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; 32BIT-DAG: BLR implicit $lr, implicit $rm, implicit $r3
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; ASM32-LABEL: .int_stack_va_arg:
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; ASM32-DAG: add 3, 4, 3
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; ASM32-DAG: add 3, 3, 5
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; ASM32-DAG: add 3, 3, 6
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; ASM32-DAG: add 3, 3, 7
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; ASM32-DAG: add 3, 3, 8
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; ASM32-DAG: add 3, 3, 9
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; ASM32-DAG: add 3, 3, 10
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; ASM32-DAG: lwz [[ARG1:[0-9]+]], 56(1)
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; ASM32-DAG: li [[ARG2:[0-9]+]], [[ARG1]]
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; ASM32-DAG: add 3, 3, [[ARG1:[0-9]+]]
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; ASM32-DAG: add 3, 3, [[ARG2:[0-9]+]]
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; ASM32-DAG: blr
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define double @double_va_arg(double %a, ...) local_unnamed_addr {
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entry:
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%arg1 = alloca i8*, align 4
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%arg2 = alloca i8*, align 4
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%0 = bitcast i8** %arg1 to i8*
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call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %0)
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%1 = bitcast i8** %arg2 to i8*
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call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %1)
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call void @llvm.va_start(i8* nonnull %0)
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call void @llvm.va_copy(i8* nonnull %1, i8* nonnull %0)
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%argp.cur = load i8*, i8** %arg1, align 4
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%argp.next = getelementptr inbounds i8, i8* %argp.cur, i32 8
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store i8* %argp.next, i8** %arg1, align 4
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%2 = bitcast i8* %argp.cur to double*
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%3 = load double, double* %2, align 4
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%add = fadd double %3, %a
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%argp.cur2 = load i8*, i8** %arg2, align 4
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%argp.next3 = getelementptr inbounds i8, i8* %argp.cur2, i32 8
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store i8* %argp.next3, i8** %arg2, align 4
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%4 = bitcast i8* %argp.cur2 to double*
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%5 = load double, double* %4, align 4
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%mul = fmul double %5, 2.000000e+00
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%add4 = fadd double %add, %mul
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call void @llvm.va_end(i8* nonnull %0)
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call void @llvm.va_end(i8* nonnull %1)
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call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %1)
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call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %0)
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ret double %add4
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}
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; 32BIT-LABEL: name: double_va_arg
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; 32BIT-LABEL: liveins:
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; 32BIT-DAG: - { reg: '$f1', virtual-reg: '' }
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; 32BIT-DAG: - { reg: '$r5', virtual-reg: '' }
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; 32BIT-DAG: - { reg: '$r6', virtual-reg: '' }
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; 32BIT-DAG: - { reg: '$r7', virtual-reg: '' }
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; 32BIT-DAG: - { reg: '$r8', virtual-reg: '' }
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; 32BIT-DAG: - { reg: '$r9', virtual-reg: '' }
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; 32BIT-DAG: - { reg: '$r10', virtual-reg: '' }
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; 32BIT-LABEL: fixedStack:
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; 32BIT-DAG: - { id: 0, type: default, offset: 32, size: 4
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; 32BIT-LABEL: stack:
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; 32BIT-DAG: - { id: 0, name: arg1, type: default, offset: 0, size: 4
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; 32BIT-DAG: - { id: 1, name: arg2, type: default, offset: 0, size: 4
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; 32BIT-LABEL: body: |
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; 32BIT-DAG: liveins: $f1, $r5, $r6, $r7, $r8, $r9, $r10
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; 32BIT-DAG: renamable $r3 = ADDI %fixed-stack.0, 0
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; 32BIT-DAG: STW renamable $r5, 0, %fixed-stack.0 :: (store 4 into %fixed-stack.0, align 16)
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; 32BIT-DAG: STW renamable $r6, 4, %fixed-stack.0 :: (store 4 into %fixed-stack.0 + 4)
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; 32BIT-DAG: STW killed renamable $r7, 8, %fixed-stack.0 :: (store 4 into %fixed-stack.0 + 8, align 8)
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; 32BIT-DAG: STW killed renamable $r8, 12, %fixed-stack.0 :: (store 4)
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; 32BIT-DAG: STW killed renamable $r9, 16, %fixed-stack.0 :: (store 4 into %fixed-stack.0 + 16, align 16)
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; 32BIT-DAG: STW killed renamable $r10, 20, %fixed-stack.0 :: (store 4)
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; 32BIT-DAG: STW renamable $r3, 0, %stack.0.arg1 :: (store 4 into %ir.0)
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; 32BIT-DAG: STW killed renamable $r3, 0, %stack.1.arg2 :: (store 4 into %ir.1)
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; 32BIT-DAG: BLR implicit $lr, implicit $rm, implicit $f1
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; ASM32-LABEL: .double_va_arg:
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; ASM32-DAG: stw 5, 32(1)
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; ASM32-DAG: stw 6, 36(1)
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; ASM32-DAG: stw 7, 40(1)
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; ASM32-DAG: stw 8, 44(1)
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; ASM32-DAG: stw 9, 48(1)
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; ASM32-DAG: stw 10, 52(1)
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; ASM32-DAG: stw [[ARG1A:[0-9]+]], -12(1)
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; ASM32-DAG: stw [[ARG1B:[0-9]+]], -16(1)
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; ASM32-DAG: stw [[ARG2A:[0-9]+]], -20(1)
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; ASM32-DAG: stw [[ARG2B:[0-9]+]], -24(1)
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; ASM32-DAG: lfd [[ARG1:[0-9]+]], -16(1)
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; ASM32-DAG: fadd 0, [[ARG1]], 1
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; ASM32-DAG: fadd 1, 1, 1
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; ASM32-DAG: lfd [[ARG2:[0-9]+]], -24(1)
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; ASM32-DAG: fadd 1, 0, [[ARG2]]
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; ASM32-DAG: blr
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define double @double_stack_va_arg(double %one, double %two, double %three, double %four, double %five, double %six, double %seven, double %eight, double %nine, double %ten, double %eleven, double %twelve, double %thirteen, ...) local_unnamed_addr {
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entry:
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%arg1 = alloca i8*, align 4
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%arg2 = alloca i8*, align 4
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%0 = bitcast i8** %arg1 to i8*
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call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %0)
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%1 = bitcast i8** %arg2 to i8*
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call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %1)
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call void @llvm.va_start(i8* nonnull %0)
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call void @llvm.va_copy(i8* nonnull %1, i8* nonnull %0)
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%add = fadd double %one, %two
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%add2 = fadd double %add, %three
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%add3 = fadd double %add2, %four
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%add4 = fadd double %add3, %five
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%add5 = fadd double %add4, %six
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%add6 = fadd double %add5, %seven
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%add7 = fadd double %add6, %eight
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%add8 = fadd double %add7, %nine
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%add9 = fadd double %add8, %ten
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%add10 = fadd double %add9, %eleven
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%add11 = fadd double %add10, %twelve
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%add12 = fadd double %add11, %thirteen
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%2 = bitcast i8** %arg1 to double**
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%argp.cur1 = load double*, double** %2, align 4
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%3 = load double, double* %argp.cur1, align 4
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%add13 = fadd double %add12, %3
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%4 = bitcast i8** %arg2 to double**
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%argp.cur142 = load double*, double** %4, align 4
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%5 = load double, double* %argp.cur142, align 4
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%mul = fmul double %5, 2.000000e+00
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%add16 = fadd double %add13, %mul
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call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %1)
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call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %0)
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ret double %add16
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}
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; 32BIT-LABEL: name: double_stack_va_arg
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; 32BIT-LABEL: liveins:
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; 32BIT-DAG: - { reg: '$f1', virtual-reg: '' }
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; 32BIT-DAG: - { reg: '$f2', virtual-reg: '' }
|
|
; 32BIT-DAG: - { reg: '$f3', virtual-reg: '' }
|
|
; 32BIT-DAG: - { reg: '$f4', virtual-reg: '' }
|
|
; 32BIT-DAG: - { reg: '$f5', virtual-reg: '' }
|
|
; 32BIT-DAG: - { reg: '$f6', virtual-reg: '' }
|
|
; 32BIT-DAG: - { reg: '$f7', virtual-reg: '' }
|
|
; 32BIT-DAG: - { reg: '$f8', virtual-reg: '' }
|
|
; 32BIT-DAG: - { reg: '$f9', virtual-reg: '' }
|
|
; 32BIT-DAG: - { reg: '$f10', virtual-reg: '' }
|
|
; 32BIT-DAG: - { reg: '$f11', virtual-reg: '' }
|
|
; 32BIT-DAG: - { reg: '$f12', virtual-reg: '' }
|
|
; 32BIT-DAG: - { reg: '$f13', virtual-reg: '' }
|
|
|
|
; 32BIT-LABEL: fixedStack:
|
|
; 32BIT-DAG: - { id: 0, type: default, offset: 128, size: 4
|
|
|
|
; 32BIT-LABEL: stack:
|
|
; 32BIT-DAG: - { id: 0, name: arg1, type: default, offset: 0, size: 4, alignment: 4,
|
|
; 32BIT-DAG: - { id: 1, name: arg2, type: default, offset: 0, size: 4, alignment: 4,
|
|
; 32BIT-DAG: - { id: 2, name: '', type: default, offset: 0, size: 8, alignment: 8,
|
|
; 32BIT-DAG: - { id: 3, name: '', type: default, offset: 0, size: 8, alignment: 8,
|
|
|
|
; 32BIT-LABEL: body: |
|
|
; 32BIT-DAG: liveins: $f1, $f2, $f3, $f4, $f5, $f6, $f7, $f8, $f9, $f10, $f11, $f12, $f13
|
|
; 32BIT-DAG: renamable $r3 = ADDI %fixed-stack.0, 0
|
|
; 32BIT-DAG: STW killed renamable $r3, 0, %stack.0.arg1 :: (store 4 into %ir.0)
|
|
; 32BIT-DAG: renamable $r3 = LWZ 0, %fixed-stack.0 :: (load 4 from %ir.argp.cur142, align 16)
|
|
; 32BIT-DAG: renamable $f1 = nofpexcept FADD killed renamable $f0, killed renamable $f1, implicit $rm
|
|
; 32BIT-DAG: renamable $f0 = nofpexcept FADD killed renamable $f1, killed renamable $f2, implicit $rm
|
|
; 32BIT-DAG: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f3, implicit $rm
|
|
; 32BIT-DAG: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f4, implicit $rm
|
|
; 32BIT-DAG: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f5, implicit $rm
|
|
; 32BIT-DAG: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f6, implicit $rm
|
|
; 32BIT-DAG: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f7, implicit $rm
|
|
; 32BIT-DAG: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f8, implicit $rm
|
|
; 32BIT-DAG: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f9, implicit $rm
|
|
; 32BIT-DAG: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f10, implicit $rm
|
|
; 32BIT-DAG: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f11, implicit $rm
|
|
; 32BIT-DAG: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f12, implicit $rm
|
|
; 32BIT-DAG: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f13, implicit $rm
|
|
; 32BIT-DAG: renamable $r4 = LWZ 4, %fixed-stack.0 :: (load 4 from %ir.argp.cur1 + 4)
|
|
; 32BIT-DAG: STW renamable $r4, 4, %stack.2 :: (store 4 into %stack.2 + 4)
|
|
; 32BIT-DAG: renamable $f1 = LFD 0, %stack.2 :: (load 8 from %stack.2)
|
|
; 32BIT-DAG: STW killed renamable $r3, 0, %stack.3 :: (store 4 into %stack.3, align 8)
|
|
; 32BIT-DAG: STW killed renamable $r4, 4, %stack.3 :: (store 4 into %stack.3 + 4)
|
|
; 32BIT-DAG: renamable $f2 = LFD 0, %stack.3 :: (load 8 from %stack.3)
|
|
; 32BIT-DAG: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f1, implicit $rm
|
|
; 32BIT-DAG: STW renamable $r3, 0, %stack.2 :: (store 4 into %stack.2, align 8)
|
|
; 32BIT-DAG: renamable $f1 = nofpexcept FADD killed renamable $f2, renamable $f2, implicit $rm
|
|
; 32BIT-DAG: BLR implicit $lr, implicit $rm, implicit $f1
|
|
|
|
; ASM32-LABEL: .double_stack_va_arg:
|
|
; ASM32-DAG: fadd 0, 1, 2
|
|
; ASM32-DAG: fadd 0, 0, 3
|
|
; ASM32-DAG: fadd 0, 0, 4
|
|
; ASM32-DAG: fadd 0, 0, 5
|
|
; ASM32-DAG: fadd 0, 0, 6
|
|
; ASM32-DAG: fadd 0, 0, 7
|
|
; ASM32-DAG: fadd 0, 0, 8
|
|
; ASM32-DAG: fadd 0, 0, 9
|
|
; ASM32-DAG: fadd 0, 0, 10
|
|
; ASM32-DAG: fadd 0, 0, 11
|
|
; ASM32-DAG: fadd 0, 0, 12
|
|
; ASM32-DAG: fadd 0, 0, 13
|
|
; ASM32-DAG: lwz [[ARG1:[0-9]+]], 128(1)
|
|
; ASM32-DAG: lwz [[ARG2:[0-9]+]], 132(1)
|
|
; ASM32-DAG: lfd [[ARG1:[0-9]+]], -16(1)
|
|
; ASM32-DAG: lfd [[ARG2:[0-9]+]], -24(1)
|
|
; ASM32-DAG: fadd 0, 0, [[ARG1]]
|
|
; ASM32-DAG: fadd [[ARG1]], 0, [[ARG2]]
|
|
; ASM32-DAG: blr
|