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289 lines
9.4 KiB
C++
289 lines
9.4 KiB
C++
//===-- AArch64Subtarget.cpp - AArch64 Subtarget Information ----*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the AArch64 specific subclass of TargetSubtarget.
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//
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//===----------------------------------------------------------------------===//
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#include "AArch64Subtarget.h"
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#include "AArch64.h"
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#include "AArch64CallLowering.h"
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#include "AArch64InstrInfo.h"
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#include "AArch64LegalizerInfo.h"
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#include "AArch64PBQPRegAlloc.h"
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#include "AArch64RegisterBankInfo.h"
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#include "AArch64TargetMachine.h"
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#include "MCTargetDesc/AArch64AddressingModes.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
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#include "llvm/CodeGen/MachineScheduler.h"
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#include "llvm/IR/GlobalValue.h"
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#include "llvm/Support/TargetParser.h"
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using namespace llvm;
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#define DEBUG_TYPE "aarch64-subtarget"
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#define GET_SUBTARGETINFO_CTOR
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#define GET_SUBTARGETINFO_TARGET_DESC
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#include "AArch64GenSubtargetInfo.inc"
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static cl::opt<bool>
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EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if "
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"converter pass"), cl::init(true), cl::Hidden);
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// If OS supports TBI, use this flag to enable it.
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static cl::opt<bool>
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UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of "
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"an address is ignored"), cl::init(false), cl::Hidden);
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static cl::opt<bool>
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UseNonLazyBind("aarch64-enable-nonlazybind",
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cl::desc("Call nonlazybind functions via direct GOT load"),
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cl::init(false), cl::Hidden);
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AArch64Subtarget &
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AArch64Subtarget::initializeSubtargetDependencies(StringRef FS,
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StringRef CPUString) {
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// Determine default and user-specified characteristics
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if (CPUString.empty())
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CPUString = "generic";
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ParseSubtargetFeatures(CPUString, FS);
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initializeProperties();
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return *this;
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}
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void AArch64Subtarget::initializeProperties() {
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// Initialize CPU specific properties. We should add a tablegen feature for
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// this in the future so we can specify it together with the subtarget
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// features.
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switch (ARMProcFamily) {
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case Others:
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break;
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case CortexA35:
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break;
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case CortexA53:
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PrefFunctionAlignment = 3;
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break;
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case CortexA55:
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break;
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case CortexA57:
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MaxInterleaveFactor = 4;
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PrefFunctionAlignment = 4;
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break;
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case CortexA72:
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case CortexA73:
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case CortexA75:
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PrefFunctionAlignment = 4;
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break;
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case Cyclone:
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CacheLineSize = 64;
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PrefetchDistance = 280;
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MinPrefetchStride = 2048;
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MaxPrefetchIterationsAhead = 3;
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break;
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case ExynosM1:
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MaxInterleaveFactor = 4;
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MaxJumpTableSize = 8;
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PrefFunctionAlignment = 4;
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PrefLoopAlignment = 3;
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break;
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case ExynosM3:
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MaxInterleaveFactor = 4;
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MaxJumpTableSize = 20;
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PrefFunctionAlignment = 5;
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PrefLoopAlignment = 4;
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break;
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case Falkor:
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MaxInterleaveFactor = 4;
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// FIXME: remove this to enable 64-bit SLP if performance looks good.
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MinVectorRegisterBitWidth = 128;
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CacheLineSize = 128;
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PrefetchDistance = 820;
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MinPrefetchStride = 2048;
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MaxPrefetchIterationsAhead = 8;
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break;
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case Kryo:
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MaxInterleaveFactor = 4;
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VectorInsertExtractBaseCost = 2;
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CacheLineSize = 128;
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PrefetchDistance = 740;
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MinPrefetchStride = 1024;
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MaxPrefetchIterationsAhead = 11;
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// FIXME: remove this to enable 64-bit SLP if performance looks good.
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MinVectorRegisterBitWidth = 128;
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break;
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case Saphira:
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MaxInterleaveFactor = 4;
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// FIXME: remove this to enable 64-bit SLP if performance looks good.
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MinVectorRegisterBitWidth = 128;
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break;
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case ThunderX2T99:
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CacheLineSize = 64;
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PrefFunctionAlignment = 3;
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PrefLoopAlignment = 2;
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MaxInterleaveFactor = 4;
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PrefetchDistance = 128;
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MinPrefetchStride = 1024;
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MaxPrefetchIterationsAhead = 4;
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// FIXME: remove this to enable 64-bit SLP if performance looks good.
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MinVectorRegisterBitWidth = 128;
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break;
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case ThunderX:
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case ThunderXT88:
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case ThunderXT81:
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case ThunderXT83:
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CacheLineSize = 128;
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PrefFunctionAlignment = 3;
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PrefLoopAlignment = 2;
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// FIXME: remove this to enable 64-bit SLP if performance looks good.
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MinVectorRegisterBitWidth = 128;
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break;
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case TSV110:
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CacheLineSize = 64;
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PrefFunctionAlignment = 4;
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PrefLoopAlignment = 2;
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break;
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}
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}
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AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
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const std::string &FS,
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const TargetMachine &TM, bool LittleEndian)
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: AArch64GenSubtargetInfo(TT, CPU, FS),
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ReserveXRegister(AArch64::GPR64commonRegClass.getNumRegs()),
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CustomCallSavedXRegs(AArch64::GPR64commonRegClass.getNumRegs()),
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IsLittle(LittleEndian),
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TargetTriple(TT), FrameLowering(),
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InstrInfo(initializeSubtargetDependencies(FS, CPU)), TSInfo(),
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TLInfo(TM, *this) {
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if (AArch64::isX18ReservedByDefault(TT))
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ReserveXRegister.set(18);
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CallLoweringInfo.reset(new AArch64CallLowering(*getTargetLowering()));
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Legalizer.reset(new AArch64LegalizerInfo(*this));
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auto *RBI = new AArch64RegisterBankInfo(*getRegisterInfo());
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// FIXME: At this point, we can't rely on Subtarget having RBI.
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// It's awkward to mix passing RBI and the Subtarget; should we pass
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// TII/TRI as well?
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InstSelector.reset(createAArch64InstructionSelector(
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*static_cast<const AArch64TargetMachine *>(&TM), *this, *RBI));
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RegBankInfo.reset(RBI);
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}
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const CallLowering *AArch64Subtarget::getCallLowering() const {
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return CallLoweringInfo.get();
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}
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const InstructionSelector *AArch64Subtarget::getInstructionSelector() const {
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return InstSelector.get();
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}
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const LegalizerInfo *AArch64Subtarget::getLegalizerInfo() const {
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return Legalizer.get();
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}
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const RegisterBankInfo *AArch64Subtarget::getRegBankInfo() const {
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return RegBankInfo.get();
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}
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/// Find the target operand flags that describe how a global value should be
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/// referenced for the current subtarget.
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unsigned char
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AArch64Subtarget::ClassifyGlobalReference(const GlobalValue *GV,
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const TargetMachine &TM) const {
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// MachO large model always goes via a GOT, simply to get a single 8-byte
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// absolute relocation on all global addresses.
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if (TM.getCodeModel() == CodeModel::Large && isTargetMachO())
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return AArch64II::MO_GOT;
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if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV)) {
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if (GV->hasDLLImportStorageClass())
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return AArch64II::MO_GOT | AArch64II::MO_DLLIMPORT;
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if (getTargetTriple().isOSWindows())
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return AArch64II::MO_GOT | AArch64II::MO_COFFSTUB;
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return AArch64II::MO_GOT;
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}
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// The small code model's direct accesses use ADRP, which cannot
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// necessarily produce the value 0 (if the code is above 4GB).
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// Same for the tiny code model, where we have a pc relative LDR.
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if ((useSmallAddressing() || TM.getCodeModel() == CodeModel::Tiny) &&
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GV->hasExternalWeakLinkage())
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return AArch64II::MO_GOT;
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return AArch64II::MO_NO_FLAG;
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}
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unsigned char AArch64Subtarget::classifyGlobalFunctionReference(
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const GlobalValue *GV, const TargetMachine &TM) const {
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// MachO large model always goes via a GOT, because we don't have the
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// relocations available to do anything else..
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if (TM.getCodeModel() == CodeModel::Large && isTargetMachO() &&
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!GV->hasInternalLinkage())
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return AArch64II::MO_GOT;
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// NonLazyBind goes via GOT unless we know it's available locally.
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auto *F = dyn_cast<Function>(GV);
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if (UseNonLazyBind && F && F->hasFnAttribute(Attribute::NonLazyBind) &&
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!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
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return AArch64II::MO_GOT;
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return AArch64II::MO_NO_FLAG;
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}
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void AArch64Subtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
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unsigned NumRegionInstrs) const {
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// LNT run (at least on Cyclone) showed reasonably significant gains for
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// bi-directional scheduling. 253.perlbmk.
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Policy.OnlyTopDown = false;
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Policy.OnlyBottomUp = false;
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// Enabling or Disabling the latency heuristic is a close call: It seems to
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// help nearly no benchmark on out-of-order architectures, on the other hand
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// it regresses register pressure on a few benchmarking.
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Policy.DisableLatencyHeuristic = DisableLatencySchedHeuristic;
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}
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bool AArch64Subtarget::enableEarlyIfConversion() const {
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return EnableEarlyIfConvert;
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}
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bool AArch64Subtarget::supportsAddressTopByteIgnored() const {
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if (!UseAddressTopByteIgnored)
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return false;
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if (TargetTriple.isiOS()) {
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unsigned Major, Minor, Micro;
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TargetTriple.getiOSVersion(Major, Minor, Micro);
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return Major >= 8;
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}
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return false;
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}
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std::unique_ptr<PBQPRAConstraint>
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AArch64Subtarget::getCustomPBQPConstraints() const {
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return balanceFPOps() ? llvm::make_unique<A57ChainingConstraint>() : nullptr;
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}
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void AArch64Subtarget::mirFileLoaded(MachineFunction &MF) const {
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// We usually compute max call frame size after ISel. Do the computation now
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// if the .mir file didn't specify it. Note that this will probably give you
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// bogus values after PEI has eliminated the callframe setup/destroy pseudo
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// instructions, specify explicitly if you need it to be correct.
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MachineFrameInfo &MFI = MF.getFrameInfo();
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if (!MFI.isMaxCallFrameSizeComputed())
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MFI.computeMaxCallFrameSize(MF);
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}
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