mirror of
https://github.com/RPCS3/llvm-mirror.git
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ae8ce1856a
llvm-svn: 19849
1005 lines
31 KiB
C++
1005 lines
31 KiB
C++
//===- AlphaISelPattern.cpp - A pattern matching inst selector for Alpha -===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines a pattern matching instruction selector for Alpha.
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//
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//===----------------------------------------------------------------------===//
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#include "Alpha.h"
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#include "AlphaRegisterInfo.h"
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#include "llvm/Constants.h" // FIXME: REMOVE
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#include "llvm/Function.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineConstantPool.h" // FIXME: REMOVE
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/ADT/Statistic.h"
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#include <set>
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// AlphaTargetLowering - Alpha Implementation of the TargetLowering interface
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namespace {
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class AlphaTargetLowering : public TargetLowering {
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int VarArgsFrameIndex; // FrameIndex for start of varargs area.
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unsigned GP; //GOT vreg
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public:
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AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM) {
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// Set up the TargetLowering object.
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addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass);
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addRegisterClass(MVT::f64, Alpha::FPRCRegisterClass);
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setOperationAction(ISD::EXTLOAD , MVT::i1 , Expand);
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setOperationAction(ISD::ZEXTLOAD , MVT::i1 , Expand);
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setOperationAction(ISD::ZEXTLOAD , MVT::i32 , Expand);
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setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand);
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setOperationAction(ISD::SEXTLOAD , MVT::i8 , Expand);
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setOperationAction(ISD::SEXTLOAD , MVT::i16 , Expand);
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setOperationAction(ISD::ZERO_EXTEND_INREG, MVT::i1, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
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// setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
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// setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
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setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
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setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
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setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
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setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
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setOperationAction(ISD::FP_TO_SINT , MVT::f32 , Promote);
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computeRegisterProperties();
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// addLegalFPImmediate(+0.0); // FLD0
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// addLegalFPImmediate(+1.0); // FLD1
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// addLegalFPImmediate(-0.0); // FLD0/FCHS
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// addLegalFPImmediate(-1.0); // FLD1/FCHS
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}
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/// LowerArguments - This hook must be implemented to indicate how we should
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/// lower the arguments for the specified function, into the specified DAG.
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virtual std::vector<SDOperand>
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LowerArguments(Function &F, SelectionDAG &DAG);
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/// LowerCallTo - This hook lowers an abstract call to a function into an
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/// actual call.
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virtual std::pair<SDOperand, SDOperand>
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LowerCallTo(SDOperand Chain, const Type *RetTy, SDOperand Callee,
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ArgListTy &Args, SelectionDAG &DAG);
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virtual std::pair<SDOperand, SDOperand>
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LowerVAStart(SDOperand Chain, SelectionDAG &DAG);
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virtual std::pair<SDOperand,SDOperand>
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LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
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const Type *ArgTy, SelectionDAG &DAG);
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virtual std::pair<SDOperand, SDOperand>
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LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
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SelectionDAG &DAG);
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void restoreGP(MachineBasicBlock* BB)
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{
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BuildMI(BB, Alpha::BIS, 2, Alpha::R29).addReg(GP).addReg(GP);
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}
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};
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}
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//http://www.cs.arizona.edu/computer.help/policy/DIGITAL_unix/AA-PY8AC-TET1_html/callCH3.html#BLOCK21
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//For now, just use variable size stack frame format
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//In a standard call, the first six items are passed in registers $16
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//- $21 and/or registers $f16 - $f21. (See Section 4.1.2 for details
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//of argument-to-register correspondence.) The remaining items are
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//collected in a memory argument list that is a naturally aligned
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//array of quadwords. In a standard call, this list, if present, must
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//be passed at 0(SP).
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//7 ... n 0(SP) ... (n-7)*8(SP)
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std::vector<SDOperand>
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AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
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{
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std::vector<SDOperand> ArgValues;
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// //#define FP $15
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// //#define RA $26
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// //#define PV $27
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// //#define GP $29
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// //#define SP $30
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// assert(0 && "TODO");
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MachineFunction &MF = DAG.getMachineFunction();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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GP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
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MachineBasicBlock& BB = MF.front();
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//Handle the return address
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//BuildMI(&BB, Alpha::IDEF, 0, Alpha::R26);
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unsigned args_int[] = {Alpha::R16, Alpha::R17, Alpha::R18,
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Alpha::R19, Alpha::R20, Alpha::R21};
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unsigned args_float[] = {Alpha::F16, Alpha::F17, Alpha::F18,
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Alpha::F19, Alpha::F20, Alpha::F21};
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std::vector<unsigned> argVreg;
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std::vector<unsigned> argPreg;
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int count = 0;
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for (Function::aiterator I = F.abegin(), E = F.aend(); I != E; ++I)
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{
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++count;
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assert(count <= 6 && "More than 6 args not supported");
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switch (getValueType(I->getType())) {
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default: std::cerr << "Unknown Type " << getValueType(I->getType()) << "\n"; abort();
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case MVT::f64:
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case MVT::f32:
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BuildMI(&BB, Alpha::IDEF, 0, args_float[count - 1]);
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argVreg.push_back(MF.getSSARegMap()->createVirtualRegister(getRegClassFor(getValueType(I->getType()))));
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argPreg.push_back(args_float[count - 1]);
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break;
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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case MVT::i64:
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BuildMI(&BB, Alpha::IDEF, 0, args_int[count - 1]);
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argVreg.push_back(MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64))));
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argPreg.push_back(args_int[count - 1]);
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break;
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}
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}
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BuildMI(&BB, Alpha::IDEF, 0, Alpha::R29);
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BuildMI(&BB, Alpha::BIS, 2, GP).addReg(Alpha::R29).addReg(Alpha::R29);
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count = 0;
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for (Function::aiterator I = F.abegin(), E = F.aend(); I != E; ++I)
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{
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SDOperand newroot;
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unsigned Opc;
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switch (getValueType(I->getType()))
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{
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default: assert(0 && "Unhandled type");
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case MVT::i64:
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case MVT::i32:
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case MVT::i16:
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case MVT::i8:
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case MVT::i1:
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Opc = Alpha::BIS;
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break;
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case MVT::f32:
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case MVT::f64:
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Opc = Alpha::CPYS;
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break;
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}
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BuildMI(&BB, Opc, 2, argVreg[count]).addReg(argPreg[count]).addReg(argPreg[count]);
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newroot = DAG.getCopyFromReg(argVreg[count], getValueType(I->getType()), DAG.getRoot());
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DAG.setRoot(newroot.getValue(1));
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ArgValues.push_back(newroot);
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++count;
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}
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return ArgValues;
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}
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std::pair<SDOperand, SDOperand>
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AlphaTargetLowering::LowerCallTo(SDOperand Chain,
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const Type *RetTy, SDOperand Callee,
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ArgListTy &Args, SelectionDAG &DAG) {
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int NumBytes = 0;
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Chain = DAG.getNode(ISD::ADJCALLSTACKDOWN, MVT::Other, Chain,
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DAG.getConstant(NumBytes, getPointerTy()));
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std::vector<SDOperand> args_to_use;
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for (unsigned i = 0, e = Args.size(); i != e; ++i)
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{
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switch (getValueType(Args[i].second)) {
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default: assert(0 && "Unexpected ValueType for argument!");
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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// Promote the integer to 64 bits. If the input type is signed use a
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// sign extend, otherwise use a zero extend.
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if (Args[i].second->isSigned())
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Args[i].first = DAG.getNode(ISD::SIGN_EXTEND_INREG, MVT::i64, Args[i].first);
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else
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Args[i].first = DAG.getNode(ISD::ZERO_EXTEND_INREG, MVT::i64, Args[i].first);
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break;
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case MVT::i64:
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break;
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}
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args_to_use.push_back(Args[i].first);
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}
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std::vector<MVT::ValueType> RetVals;
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MVT::ValueType RetTyVT = getValueType(RetTy);
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if (RetTyVT != MVT::isVoid)
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RetVals.push_back(RetTyVT);
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RetVals.push_back(MVT::Other);
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SDOperand TheCall = SDOperand(DAG.getCall(RetVals, Chain, Callee, args_to_use), 0);
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Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
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Chain = DAG.getNode(ISD::ADJCALLSTACKUP, MVT::Other, Chain,
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DAG.getConstant(NumBytes, getPointerTy()));
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return std::make_pair(TheCall, Chain);
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}
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std::pair<SDOperand, SDOperand>
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AlphaTargetLowering::LowerVAStart(SDOperand Chain, SelectionDAG &DAG) {
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//vastart just returns the address of the VarArgsFrameIndex slot.
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return std::make_pair(DAG.getFrameIndex(VarArgsFrameIndex, MVT::i64), Chain);
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}
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std::pair<SDOperand,SDOperand> AlphaTargetLowering::
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LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
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const Type *ArgTy, SelectionDAG &DAG) {
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abort();
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}
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std::pair<SDOperand, SDOperand> AlphaTargetLowering::
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LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
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SelectionDAG &DAG) {
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abort();
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}
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namespace {
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//===--------------------------------------------------------------------===//
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/// ISel - Alpha specific code to select Alpha machine instructions for
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/// SelectionDAG operations.
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///
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class ISel : public SelectionDAGISel {
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/// AlphaLowering - This object fully describes how to lower LLVM code to an
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/// Alpha-specific SelectionDAG.
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AlphaTargetLowering AlphaLowering;
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/// ExprMap - As shared expressions are codegen'd, we keep track of which
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/// vreg the value is produced in, so we only emit one copy of each compiled
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/// tree.
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std::map<SDOperand, unsigned> ExprMap;
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std::set<SDOperand> LoweredTokens;
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public:
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ISel(TargetMachine &TM) : SelectionDAGISel(AlphaLowering), AlphaLowering(TM) {
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}
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/// InstructionSelectBasicBlock - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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virtual void InstructionSelectBasicBlock(SelectionDAG &DAG) {
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// Codegen the basic block.
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Select(DAG.getRoot());
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// Clear state used for selection.
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ExprMap.clear();
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LoweredTokens.clear();
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}
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unsigned SelectExpr(SDOperand N);
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void Select(SDOperand N);
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};
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}
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unsigned ISel::SelectExpr(SDOperand N) {
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unsigned Result;
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unsigned Tmp1, Tmp2, Tmp3;
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unsigned Opc = 0;
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SDNode *Node = N.Val;
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unsigned &Reg = ExprMap[N];
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if (Reg) return Reg;
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if (N.getOpcode() != ISD::CALL)
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Reg = Result = (N.getValueType() != MVT::Other) ?
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MakeReg(N.getValueType()) : 1;
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else {
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// If this is a call instruction, make sure to prepare ALL of the result
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// values as well as the chain.
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if (Node->getNumValues() == 1)
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Reg = Result = 1; // Void call, just a chain.
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else {
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Result = MakeReg(Node->getValueType(0));
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ExprMap[N.getValue(0)] = Result;
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for (unsigned i = 1, e = N.Val->getNumValues()-1; i != e; ++i)
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ExprMap[N.getValue(i)] = MakeReg(Node->getValueType(i));
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ExprMap[SDOperand(Node, Node->getNumValues()-1)] = 1;
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}
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}
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switch (N.getOpcode()) {
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default:
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Node->dump();
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assert(0 && "Node not handled!\n");
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case ISD::FrameIndex:
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Tmp1 = cast<FrameIndexSDNode>(N)->getIndex();
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BuildMI(BB, Alpha::LDA, 2, Result).addImm(Tmp1 * 8).addReg(Alpha::R30);
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return Result;
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case ISD::EXTLOAD:
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// Make sure we generate both values.
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if (Result != 1)
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ExprMap[N.getValue(1)] = 1; // Generate the token
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else
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Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
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Select(Node->getOperand(0)); // chain
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Tmp1 = SelectExpr(Node->getOperand(1));
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switch(Node->getValueType(0)) {
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default: Node->dump(); assert(0 && "Unknown type to sign extend to.");
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case MVT::i64:
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switch (cast<MVTSDNode>(Node)->getExtraValueType()) {
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default:
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Node->dump();
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assert(0 && "Bad extend load!");
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case MVT::i64:
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BuildMI(BB, Alpha::LDQ, 2, Result).addImm(0).addReg(Tmp1);
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break;
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case MVT::i32:
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BuildMI(BB, Alpha::LDL, 2, Result).addImm(0).addReg(Tmp1);
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break;
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case MVT::i16:
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BuildMI(BB, Alpha::LDWU, 2, Result).addImm(0).addReg(Tmp1);
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break;
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case MVT::i8:
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case MVT::i1: //FIXME: DAG does not expand i8??
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BuildMI(BB, Alpha::LDBU, 2, Result).addImm(0).addReg(Tmp1);
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break;
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}
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break;
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}
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return Result;
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case ISD::SEXTLOAD:
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// Make sure we generate both values.
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if (Result != 1)
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ExprMap[N.getValue(1)] = 1; // Generate the token
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else
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Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
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Select(Node->getOperand(0)); // chain
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Tmp1 = SelectExpr(Node->getOperand(1));
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switch(Node->getValueType(0)) {
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default: Node->dump(); assert(0 && "Unknown type to sign extend to.");
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case MVT::i64:
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switch (cast<MVTSDNode>(Node)->getExtraValueType()) {
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default:
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Node->dump();
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assert(0 && "Bad sign extend!");
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case MVT::i32:
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BuildMI(BB, Alpha::LDL, 2, Result).addImm(0).addReg(Tmp1);
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break;
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// case MVT::i16:
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// BuildMI(BB, Alpha::LDW, 2, Result).addImm(0).addReg(Tmp1);
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// break;
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// case MVT::i8:
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// BuildMI(BB, Alpha::LDB, 2, Result).addImm(0).addReg(Tmp1);
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// break;
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}
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break;
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}
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return Result;
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case ISD::ZEXTLOAD:
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// Make sure we generate both values.
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if (Result != 1)
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ExprMap[N.getValue(1)] = 1; // Generate the token
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else
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Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
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Select(Node->getOperand(0)); // chain
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Tmp1 = SelectExpr(Node->getOperand(1));
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switch(Node->getValueType(0)) {
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default: Node->dump(); assert(0 && "Unknown type to zero extend to.");
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case MVT::i64:
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switch (cast<MVTSDNode>(Node)->getExtraValueType()) {
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default:
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Node->dump();
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assert(0 && "Bad sign extend!");
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case MVT::i16:
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BuildMI(BB, Alpha::LDWU, 2, Result).addImm(0).addReg(Tmp1);
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break;
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case MVT::i8:
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BuildMI(BB, Alpha::LDBU, 2, Result).addImm(0).addReg(Tmp1);
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break;
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}
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break;
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}
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return Result;
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case ISD::GlobalAddress:
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AlphaLowering.restoreGP(BB);
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BuildMI(BB, Alpha::LOAD_ADDR, 1, Result)
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.addGlobalAddress(cast<GlobalAddressSDNode>(N)->getGlobal());
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return Result;
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case ISD::CALL:
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{
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Select(N.getOperand(0));
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// The chain for this call is now lowered.
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ExprMap.insert(std::make_pair(N.getValue(Node->getNumValues()-1), 1));
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//grab the arguments
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std::vector<unsigned> argvregs;
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assert(Node->getNumOperands() < 8 && "Only 6 args supported");
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for(int i = 2, e = Node->getNumOperands(); i < e; ++i)
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argvregs.push_back(SelectExpr(N.getOperand(i)));
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for(int i = 0, e = argvregs.size(); i < e; ++i)
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{
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unsigned args_int[] = {Alpha::R16, Alpha::R17, Alpha::R18,
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Alpha::R19, Alpha::R20, Alpha::R21};
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unsigned args_float[] = {Alpha::F16, Alpha::F17, Alpha::F18,
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Alpha::F19, Alpha::F20, Alpha::F21};
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switch(N.getOperand(i).getValueType()) {
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default: Node->dump(); assert(0 && "Unknown value type for call");
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
|
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case MVT::i64:
|
|
BuildMI(BB, Alpha::BIS, 2, args_int[i]).addReg(argvregs[i]).addReg(argvregs[i]);
|
|
break;
|
|
case MVT::f32:
|
|
case MVT::f64:
|
|
BuildMI(BB, Alpha::CPYS, 2, args_float[i]).addReg(argvregs[i]).addReg(argvregs[i]);
|
|
break;
|
|
}
|
|
|
|
}
|
|
//build the right kind of call
|
|
if (GlobalAddressSDNode *GASD =
|
|
dyn_cast<GlobalAddressSDNode>(N.getOperand(1)))
|
|
{
|
|
Select(N.getOperand(0));
|
|
AlphaLowering.restoreGP(BB);
|
|
BuildMI(BB, Alpha::CALL, 1).addGlobalAddress(GASD->getGlobal(),true);
|
|
}
|
|
else if (ExternalSymbolSDNode *ESSDN =
|
|
dyn_cast<ExternalSymbolSDNode>(N.getOperand(1)))
|
|
{
|
|
Select(N.getOperand(0));
|
|
AlphaLowering.restoreGP(BB);
|
|
BuildMI(BB, Alpha::CALL, 0).addExternalSymbol(ESSDN->getSymbol(), true);
|
|
}
|
|
else
|
|
{
|
|
Select(N.getOperand(0));
|
|
Tmp1 = SelectExpr(N.getOperand(1));
|
|
BuildMI(BB, Alpha::CALL, 1).addReg(Tmp1);
|
|
AlphaLowering.restoreGP(BB);
|
|
}
|
|
|
|
//push the result into a virtual register
|
|
// if (Result != 1)
|
|
// BuildMI(BB, Alpha::BIS, 2, Result).addReg(Alpha::R0).addReg(Alpha::R0);
|
|
|
|
switch (Node->getValueType(0)) {
|
|
default: Node->dump(); assert(0 && "Unknown value type for call result!");
|
|
case MVT::Other: return 1;
|
|
case MVT::i1:
|
|
case MVT::i8:
|
|
case MVT::i16:
|
|
case MVT::i32:
|
|
case MVT::i64:
|
|
BuildMI(BB, Alpha::BIS, 2, Result).addReg(Alpha::R0).addReg(Alpha::R0);
|
|
break;
|
|
case MVT::f32:
|
|
case MVT::f64:
|
|
BuildMI(BB, Alpha::CPYS, 2, Result).addReg(Alpha::F0).addReg(Alpha::F0);
|
|
break;
|
|
}
|
|
return Result+N.ResNo;
|
|
}
|
|
|
|
case ISD::SIGN_EXTEND:
|
|
case ISD::SIGN_EXTEND_INREG:
|
|
{
|
|
Tmp1 = SelectExpr(N.getOperand(0));
|
|
MVTSDNode* MVN = dyn_cast<MVTSDNode>(Node);
|
|
//std::cerr << "SrcT: " << MVN->getExtraValueType() << "\n";
|
|
switch(MVN->getExtraValueType())
|
|
{
|
|
default:
|
|
Node->dump();
|
|
assert(0 && "Sign Extend InReg not there yet");
|
|
break;
|
|
case MVT::i32:
|
|
{
|
|
BuildMI(BB, Alpha::ADDLi, 2, Result).addReg(Tmp1).addImm(0);
|
|
break;
|
|
}
|
|
case MVT::i16:
|
|
BuildMI(BB, Alpha::SEXTW, 1, Result).addReg(Tmp1);
|
|
break;
|
|
case MVT::i8:
|
|
BuildMI(BB, Alpha::SEXTB, 1, Result).addReg(Tmp1);
|
|
break;
|
|
}
|
|
return Result;
|
|
}
|
|
case ISD::ZERO_EXTEND_INREG:
|
|
{
|
|
Tmp1 = SelectExpr(N.getOperand(0));
|
|
MVTSDNode* MVN = dyn_cast<MVTSDNode>(Node);
|
|
//std::cerr << "SrcT: " << MVN->getExtraValueType() << "\n";
|
|
switch(MVN->getExtraValueType())
|
|
{
|
|
default:
|
|
Node->dump();
|
|
assert(0 && "Zero Extend InReg not there yet");
|
|
break;
|
|
case MVT::i32: Tmp2 = 0xf0; break;
|
|
case MVT::i16: Tmp2 = 0xfc; break;
|
|
case MVT::i8: Tmp2 = 0xfe; break;
|
|
}
|
|
BuildMI(BB, Alpha::ZAPi, 2, Result).addReg(Tmp1).addImm(Tmp2);
|
|
return Result;
|
|
}
|
|
|
|
case ISD::SETCC:
|
|
Tmp1 = SelectExpr(N.getOperand(0));
|
|
Tmp2 = SelectExpr(N.getOperand(1));
|
|
if (SetCCSDNode *SetCC = dyn_cast<SetCCSDNode>(Node)) {
|
|
if (MVT::isInteger(SetCC->getOperand(0).getValueType())) {
|
|
switch (SetCC->getCondition()) {
|
|
default: Node->dump(); assert(0 && "Unknown integer comparison!");
|
|
case ISD::SETEQ:
|
|
BuildMI(BB, Alpha::CMPEQ, 2, Result).addReg(Tmp1).addReg(Tmp2);
|
|
break;
|
|
case ISD::SETGT:
|
|
BuildMI(BB, Alpha::CMPLT, 2, Result).addReg(Tmp2).addReg(Tmp1);
|
|
break;
|
|
case ISD::SETGE:
|
|
BuildMI(BB, Alpha::CMPLE, 2, Result).addReg(Tmp2).addReg(Tmp1);
|
|
break;
|
|
case ISD::SETLT:
|
|
BuildMI(BB, Alpha::CMPLT, 2, Result).addReg(Tmp1).addReg(Tmp2);
|
|
break;
|
|
case ISD::SETLE:
|
|
BuildMI(BB, Alpha::CMPLE, 2, Result).addReg(Tmp1).addReg(Tmp2);
|
|
break;
|
|
case ISD::SETNE:
|
|
{
|
|
unsigned Tmp3 = MakeReg(MVT::i64);
|
|
BuildMI(BB, Alpha::CMPEQ, 2, Tmp3).addReg(Tmp1).addReg(Tmp2);
|
|
BuildMI(BB, Alpha::CMPEQ, 2, Result).addReg(Tmp3).addReg(Alpha::R31);
|
|
break;
|
|
}
|
|
case ISD::SETULT:
|
|
BuildMI(BB, Alpha::CMPULT, 2, Result).addReg(Tmp1).addReg(Tmp2);
|
|
break;
|
|
case ISD::SETUGT:
|
|
BuildMI(BB, Alpha::CMPULT, 2, Result).addReg(Tmp2).addReg(Tmp1);
|
|
break;
|
|
case ISD::SETULE:
|
|
BuildMI(BB, Alpha::CMPULE, 2, Result).addReg(Tmp1).addReg(Tmp2);
|
|
break;
|
|
case ISD::SETUGE:
|
|
BuildMI(BB, Alpha::CMPULE, 2, Result).addReg(Tmp2).addReg(Tmp1);
|
|
break;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
Node->dump();
|
|
assert(0 && "only integer");
|
|
}
|
|
}
|
|
else
|
|
{
|
|
Node->dump();
|
|
assert(0 && "Not a setcc in setcc");
|
|
}
|
|
return Result;
|
|
|
|
case ISD::CopyFromReg:
|
|
{
|
|
if (Result == 1)
|
|
Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
|
|
|
|
SDOperand Chain = N.getOperand(0);
|
|
|
|
Select(Chain);
|
|
unsigned r = dyn_cast<RegSDNode>(Node)->getReg();
|
|
//std::cerr << "CopyFromReg " << Result << " = " << r << "\n";
|
|
BuildMI(BB, Alpha::BIS, 2, Result).addReg(r).addReg(r);
|
|
return Result;
|
|
}
|
|
|
|
//Most of the plain arithmetic and logic share the same form, and the same
|
|
//constant immediate test
|
|
case ISD::AND:
|
|
case ISD::OR:
|
|
case ISD::XOR:
|
|
case ISD::SHL:
|
|
case ISD::SRL:
|
|
case ISD::MUL:
|
|
switch (N.getValueType()) {
|
|
default: Node->dump(); assert (0 && "unhandled type");
|
|
case MVT::f64:
|
|
assert(N.getOpcode() == ISD::MUL && "only mul here please");
|
|
Tmp1 = SelectExpr(N.getOperand(0));
|
|
Tmp2 = SelectExpr(N.getOperand(1));
|
|
BuildMI(BB, Alpha::MULT, 2, Result).addReg(Tmp1).addReg(Tmp2);
|
|
break;
|
|
case MVT::f32:
|
|
assert(N.getOpcode() == ISD::MUL && "only mul here please");
|
|
Tmp1 = SelectExpr(N.getOperand(0));
|
|
Tmp2 = SelectExpr(N.getOperand(1));
|
|
BuildMI(BB, Alpha::MULS, 2, Result).addReg(Tmp1).addReg(Tmp2);
|
|
break;
|
|
case MVT::i64:
|
|
if(N.getOperand(1).getOpcode() == ISD::Constant &&
|
|
cast<ConstantSDNode>(N.getOperand(1))->getValue() >= 0 &&
|
|
cast<ConstantSDNode>(N.getOperand(1))->getValue() <= 255)
|
|
{
|
|
switch(N.getOpcode()) {
|
|
case ISD::AND: Opc = Alpha::ANDi; break;
|
|
case ISD::OR: Opc = Alpha::BISi; break;
|
|
case ISD::XOR: Opc = Alpha::XORi; break;
|
|
case ISD::SHL: Opc = Alpha::SLi; break;
|
|
case ISD::SRL: Opc = Alpha::SRLi; break;
|
|
case ISD::SRA: Opc = Alpha::SRAi; break;
|
|
case ISD::MUL: Opc = Alpha::MULQi; break;
|
|
};
|
|
Tmp1 = SelectExpr(N.getOperand(0));
|
|
Tmp2 = cast<ConstantSDNode>(N.getOperand(1))->getValue();
|
|
BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(Tmp2);
|
|
}
|
|
else
|
|
{
|
|
switch(N.getOpcode()) {
|
|
case ISD::AND: Opc = Alpha::AND; break;
|
|
case ISD::OR: Opc = Alpha::BIS; break;
|
|
case ISD::XOR: Opc = Alpha::XOR; break;
|
|
case ISD::SHL: Opc = Alpha::SL; break;
|
|
case ISD::SRL: Opc = Alpha::SRL; break;
|
|
case ISD::SRA: Opc = Alpha::SRA; break;
|
|
case ISD::MUL: Opc = Alpha::MULQ; break;
|
|
};
|
|
Tmp1 = SelectExpr(N.getOperand(0));
|
|
Tmp2 = SelectExpr(N.getOperand(1));
|
|
BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
|
|
}
|
|
break;
|
|
}
|
|
return Result;
|
|
|
|
case ISD::ADD:
|
|
case ISD::SUB:
|
|
{
|
|
bool isAdd = N.getOpcode() == ISD::ADD;
|
|
|
|
switch (N.getValueType()) {
|
|
default: Node->dump(); assert(0 && "Unhandled type");
|
|
case MVT::i64: {
|
|
//FIXME: first check for Scaled Adds and Subs!
|
|
if(N.getOperand(1).getOpcode() == ISD::Constant &&
|
|
cast<ConstantSDNode>(N.getOperand(1))->getValue() >= 0 &&
|
|
cast<ConstantSDNode>(N.getOperand(1))->getValue() <= 255)
|
|
{ //Normal imm add/sub
|
|
Opc = isAdd ? Alpha::ADDQi : Alpha::SUBQi;
|
|
Tmp1 = SelectExpr(N.getOperand(0));
|
|
Tmp2 = cast<ConstantSDNode>(N.getOperand(1))->getValue();
|
|
BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(Tmp2);
|
|
}
|
|
else if(N.getOperand(1).getOpcode() == ISD::Constant &&
|
|
cast<ConstantSDNode>(N.getOperand(1))->getValue() >= 0 &&
|
|
cast<ConstantSDNode>(N.getOperand(1))->getValue() <= 32767)
|
|
{ //LDA //FIXME: expand the above condition a bit
|
|
Tmp1 = SelectExpr(N.getOperand(0));
|
|
Tmp2 = cast<ConstantSDNode>(N.getOperand(1))->getValue();
|
|
if (!isAdd)
|
|
Tmp2 = -Tmp2;
|
|
BuildMI(BB, Alpha::LDA, 2, Result).addImm(Tmp2).addReg(Tmp1);
|
|
}
|
|
else
|
|
{ //Normal add/sub
|
|
Opc = isAdd ? Alpha::ADDQ : Alpha::SUBQ;
|
|
Tmp1 = SelectExpr(N.getOperand(0));
|
|
Tmp2 = SelectExpr(N.getOperand(1));
|
|
BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
|
|
}
|
|
} break;
|
|
case MVT::f64:
|
|
case MVT::f32:
|
|
if (N.getValueType() == MVT::f64)
|
|
Opc = isAdd ? Alpha::ADDT : Alpha::SUBT;
|
|
else
|
|
Opc = isAdd ? Alpha::ADDS : Alpha::SUBS;
|
|
//
|
|
Tmp1 = SelectExpr(N.getOperand(0));
|
|
Tmp2 = SelectExpr(N.getOperand(1));
|
|
BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
|
|
break;
|
|
}
|
|
return Result;
|
|
}
|
|
|
|
case ISD::UREM:
|
|
case ISD::SREM:
|
|
case ISD::SDIV:
|
|
case ISD::UDIV:
|
|
switch (N.getValueType()) {
|
|
default: Node->dump(); assert (0 && "unhandled type");
|
|
case MVT::f64:
|
|
assert(N.getOpcode() == ISD::SDIV && "only div here please");
|
|
Opc = Alpha::DIVT;
|
|
break;
|
|
case MVT::f32:
|
|
assert(N.getOpcode() == ISD::SDIV && "only div here please");
|
|
Opc = Alpha::DIVS;
|
|
break;
|
|
case MVT::i64:
|
|
//FIXME: alpha really doesn't support any of these operations,
|
|
// the ops are expanded into special library calls with
|
|
// special calling conventions
|
|
switch(N.getOpcode()) {
|
|
case ISD::UREM: Opc = Alpha::REMQU; break;
|
|
case ISD::SREM: Opc = Alpha::REMQ; break;
|
|
case ISD::UDIV: Opc = Alpha::DIVQU; break;
|
|
case ISD::SDIV: Opc = Alpha::DIVQ; break;
|
|
}
|
|
break;
|
|
}
|
|
Tmp1 = SelectExpr(N.getOperand(0));
|
|
Tmp2 = SelectExpr(N.getOperand(1));
|
|
BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
|
|
return Result;
|
|
|
|
// case ISD::SINT_TO_FP:
|
|
// MVT::ValueType DestTy = N.getValueType();
|
|
// Tmp1 = SelectExpr(N.getOperand(0)); // Get the operand register
|
|
// Tmp2 = MakeReg(DestTy);
|
|
// Opc = DestTy == MVT::f64 ? ITOFT : ITOFS;
|
|
// BuildMI(BB, Opc, 1, Tmp2).addReg(Tmp1);
|
|
// Opc = DestTy == MVT::f64 ? CVTQT : CVTQS;
|
|
// BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
|
|
// // case ISD::UINT_TO_FP:
|
|
|
|
// case ISD::FP_TO_SINT:
|
|
// assert (N.getValueType() == MVT::f64 && "Only can convert for doubles");
|
|
// Tmp1 = SelectExpr(N.getOperand(0)); // Get the operand register
|
|
// Tmp2 = MakeReg(SrcTy);
|
|
// BuildMI(BB, CVTTQ, 1, Tmp2).addReg(Tmp1);
|
|
// BuildMI(BB, FTOIT, 1, Result).addReg(Tmp2);
|
|
// return result;
|
|
|
|
// // case ISD::FP_TO_UINT:
|
|
|
|
case ISD::SELECT:
|
|
{
|
|
Tmp2 = SelectExpr(N.getOperand(1)); //Use if TRUE
|
|
Tmp3 = SelectExpr(N.getOperand(2)); //Use if FALSE
|
|
Tmp1 = SelectExpr(N.getOperand(0)); //Cond
|
|
// Get the condition into the zero flag.
|
|
unsigned dummy = MakeReg(MVT::i64);
|
|
BuildMI(BB, Alpha::BIS, 2, dummy).addReg(Tmp3).addReg(Tmp3);
|
|
BuildMI(BB, Alpha::CMOVEQ, 2, Result).addReg(Tmp2).addReg(Tmp1);
|
|
return Result;
|
|
}
|
|
|
|
case ISD::Constant:
|
|
{
|
|
long val = cast<ConstantSDNode>(N)->getValue();
|
|
BuildMI(BB, Alpha::LOAD_IMM, 1, Result).addImm(val);
|
|
return Result;
|
|
}
|
|
|
|
case ISD::LOAD:
|
|
{
|
|
// Make sure we generate both values.
|
|
if (Result != 1)
|
|
ExprMap[N.getValue(1)] = 1; // Generate the token
|
|
else
|
|
Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
|
|
|
|
SDOperand Chain = N.getOperand(0);
|
|
SDOperand Address = N.getOperand(1);
|
|
|
|
if (Address.getOpcode() == ISD::GlobalAddress)
|
|
{
|
|
Select(Chain);
|
|
AlphaLowering.restoreGP(BB);
|
|
BuildMI(BB, Alpha::LOAD, 1, Result).addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
|
|
}
|
|
else
|
|
{
|
|
Select(Chain);
|
|
Tmp2 = SelectExpr(Address);
|
|
BuildMI(BB, Alpha::LDQ, 2, Result).addImm(0).addReg(Tmp2);
|
|
}
|
|
return Result;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
void ISel::Select(SDOperand N) {
|
|
unsigned Tmp1, Tmp2, Opc;
|
|
|
|
// FIXME: Disable for our current expansion model!
|
|
if (/*!N->hasOneUse() &&*/ !LoweredTokens.insert(N).second)
|
|
return; // Already selected.
|
|
|
|
SDNode *Node = N.Val;
|
|
|
|
switch (N.getOpcode()) {
|
|
|
|
default:
|
|
Node->dump(); std::cerr << "\n";
|
|
assert(0 && "Node not handled yet!");
|
|
|
|
case ISD::BRCOND: {
|
|
MachineBasicBlock *Dest =
|
|
cast<BasicBlockSDNode>(N.getOperand(2))->getBasicBlock();
|
|
|
|
Select(N.getOperand(0));
|
|
Tmp1 = SelectExpr(N.getOperand(1));
|
|
BuildMI(BB, Alpha::BNE, 2).addReg(Tmp1).addMBB(Dest);
|
|
return;
|
|
}
|
|
|
|
case ISD::BR: {
|
|
MachineBasicBlock *Dest =
|
|
cast<BasicBlockSDNode>(N.getOperand(1))->getBasicBlock();
|
|
|
|
Select(N.getOperand(0));
|
|
BuildMI(BB, Alpha::BR, 1, Alpha::R31).addMBB(Dest);
|
|
return;
|
|
}
|
|
|
|
case ISD::ImplicitDef:
|
|
Select(N.getOperand(0));
|
|
BuildMI(BB, Alpha::IDEF, 0, cast<RegSDNode>(N)->getReg());
|
|
return;
|
|
|
|
case ISD::EntryToken: return; // Noop
|
|
|
|
case ISD::TokenFactor:
|
|
for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
|
|
Select(Node->getOperand(i));
|
|
|
|
//N.Val->dump(); std::cerr << "\n";
|
|
//assert(0 && "Node not handled yet!");
|
|
|
|
return;
|
|
|
|
case ISD::CopyToReg:
|
|
Select(N.getOperand(0));
|
|
Tmp1 = SelectExpr(N.getOperand(1));
|
|
Tmp2 = cast<RegSDNode>(N)->getReg();
|
|
|
|
if (Tmp1 != Tmp2) {
|
|
BuildMI(BB, Alpha::BIS, 2, Tmp2).addReg(Tmp1).addReg(Tmp1);
|
|
}
|
|
return;
|
|
|
|
case ISD::RET:
|
|
switch (N.getNumOperands()) {
|
|
default:
|
|
std::cerr << N.getNumOperands() << "\n";
|
|
for (unsigned i = 0; i < N.getNumOperands(); ++i)
|
|
std::cerr << N.getOperand(i).getValueType() << "\n";
|
|
Node->dump();
|
|
assert(0 && "Unknown return instruction!");
|
|
case 2:
|
|
Select(N.getOperand(0));
|
|
Tmp1 = SelectExpr(N.getOperand(1));
|
|
switch (N.getOperand(1).getValueType()) {
|
|
default: Node->dump(); assert(0 && "All other types should have been promoted!!");
|
|
case MVT::f64:
|
|
case MVT::f32:
|
|
BuildMI(BB, Alpha::CPYS, 2, Alpha::F0).addReg(Tmp1).addReg(Tmp1);
|
|
break;
|
|
case MVT::i32:
|
|
case MVT::i64:
|
|
BuildMI(BB, Alpha::BIS, 2, Alpha::R0).addReg(Tmp1).addReg(Tmp1);
|
|
break;
|
|
}
|
|
break;
|
|
case 1:
|
|
Select(N.getOperand(0));
|
|
break;
|
|
}
|
|
//Tmp2 = AlphaLowering.getRetAddr();
|
|
//BuildMI(BB, Alpha::BIS, 2, Alpha::R26).addReg(Tmp2).addReg(Tmp2);
|
|
BuildMI(BB, Alpha::RETURN, 0); // Just emit a 'ret' instruction
|
|
return;
|
|
|
|
case ISD::STORE:
|
|
Select(N.getOperand(0));
|
|
Tmp1 = SelectExpr(N.getOperand(1)); //value
|
|
if (N.getOperand(2).getOpcode() == ISD::GlobalAddress)
|
|
{
|
|
AlphaLowering.restoreGP(BB);
|
|
BuildMI(BB, Alpha::STORE, 2).addReg(Tmp1).addGlobalAddress(cast<GlobalAddressSDNode>(N.getOperand(2))->getGlobal());
|
|
}
|
|
else
|
|
{
|
|
Tmp2 = SelectExpr(N.getOperand(2)); //address
|
|
BuildMI(BB, Alpha::STQ, 3).addReg(Tmp1).addImm(0).addReg(Tmp2);
|
|
}
|
|
return;
|
|
|
|
case ISD::EXTLOAD:
|
|
case ISD::SEXTLOAD:
|
|
case ISD::ZEXTLOAD:
|
|
case ISD::LOAD:
|
|
case ISD::CopyFromReg:
|
|
case ISD::CALL:
|
|
// case ISD::DYNAMIC_STACKALLOC:
|
|
SelectExpr(N);
|
|
return;
|
|
|
|
|
|
case ISD::TRUNCSTORE: { // truncstore chain, val, ptr :storety
|
|
MVT::ValueType StoredTy = cast<MVTSDNode>(Node)->getExtraValueType();
|
|
if (StoredTy == MVT::i64) {
|
|
Node->dump();
|
|
assert(StoredTy != MVT::i64 && "Unsupported TRUNCSTORE for this target!");
|
|
}
|
|
|
|
Select(N.getOperand(0));
|
|
Tmp1 = SelectExpr(N.getOperand(1));
|
|
Tmp2 = SelectExpr(N.getOperand(2));
|
|
|
|
switch (StoredTy) {
|
|
default: Node->dump(); assert(0 && "Unhandled Type"); break;
|
|
case MVT::i1: //FIXME: DAG does not promote this load
|
|
case MVT::i8: Opc = Alpha::STB; break;
|
|
case MVT::i16: Opc = Alpha::STW; break;
|
|
case MVT::i32: Opc = Alpha::STL; break;
|
|
}
|
|
|
|
BuildMI(BB, Opc, 2).addReg(Tmp1).addImm(0).addReg(Tmp2);
|
|
return;
|
|
}
|
|
|
|
case ISD::ADJCALLSTACKDOWN:
|
|
case ISD::ADJCALLSTACKUP:
|
|
Select(N.getOperand(0));
|
|
Tmp1 = cast<ConstantSDNode>(N.getOperand(1))->getValue();
|
|
|
|
Opc = N.getOpcode() == ISD::ADJCALLSTACKDOWN ? Alpha::ADJUSTSTACKDOWN :
|
|
Alpha::ADJUSTSTACKUP;
|
|
BuildMI(BB, Opc, 1).addImm(Tmp1);
|
|
return;
|
|
}
|
|
assert(0 && "Should not be reached!");
|
|
}
|
|
|
|
|
|
/// createAlphaPatternInstructionSelector - This pass converts an LLVM function
|
|
/// into a machine code representation using pattern matching and a machine
|
|
/// description file.
|
|
///
|
|
FunctionPass *llvm::createAlphaPatternInstructionSelector(TargetMachine &TM) {
|
|
return new ISel(TM);
|
|
}
|