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AArch64
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[AArch64]Merge halfword loads into a 32-bit load
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2015-10-19 18:34:53 +00:00 |
AMDGPU
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DAGCombiner: Don't stop finding better chain on 2 aliases
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2015-10-13 00:49:00 +00:00 |
ARM
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Fix mapping of @llvm.arm.ssat/usat intrinsics to ssat/usat instructions
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2015-10-19 11:44:24 +00:00 |
BPF
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[bpf] Do not expand UNDEF SDNode during insn selection lowering
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2015-10-08 18:52:40 +00:00 |
CPP
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Generic
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[Hexagon] Reverting test file change.
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2015-10-17 01:58:51 +00:00 |
Hexagon
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[Hexagon] Delay emission of CFI instructions
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2015-10-19 17:46:01 +00:00 |
Inputs
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Mips
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[mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE.
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2015-10-15 14:34:23 +00:00 |
MIR
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[mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE.
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2015-10-15 14:34:23 +00:00 |
MSP430
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NVPTX
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PowerPC
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[MachO] Stop generating *coal* sections.
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2015-10-15 05:28:38 +00:00 |
SPARC
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Fix assert when emitting llvm.pow.f86.
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2015-10-09 21:36:19 +00:00 |
SystemZ
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[SystemZ] CodeGen/SystemZ/asm-18.ll run with -verify-machineinstrs
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2015-10-10 07:20:23 +00:00 |
Thumb
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[ARM] Modify codegen for memcpy intrinsic to prefer LDM/STM.
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2015-10-05 14:49:54 +00:00 |
Thumb2
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[ARM] Use correct half-precision functions in EABI mode
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2015-10-07 16:58:49 +00:00 |
WebAssembly
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WebAssembly: fix syntax for br_if.
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2015-10-20 00:37:42 +00:00 |
WinEH
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[WinEH] Fix eh.exceptionpointer intrinsic lowering
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2015-10-17 00:08:08 +00:00 |
X86
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Enhance loop rotation with existence of profile data in MachineBlockPlacement pass.
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2015-10-19 23:16:40 +00:00 |
XCore
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