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307b53fe55
A couple of old test cases in test/MC/PowerPC were still using LLVM IR. Now that we have a working assembler, we can move them to assembler tests instead: ppc64-initial-cfa.ll ppc64-relocs-01.ll ppc64-tls-relocs-01.ll llvm-svn: 183829
47 lines
1.4 KiB
ArmAsm
47 lines
1.4 KiB
ArmAsm
# RUN: llvm-mc -triple=powerpc64-unknown-linux-gnu -filetype=obj %s | \
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# RUN: llvm-readobj -r | FileCheck %s
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.section .opd,"aw",@progbits
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access_int64:
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.quad .L.access_int64
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.quad .TOC.@tocbase
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.quad 0
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.text
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.L.access_int64:
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ld 4, .LC1@toc(2)
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bl sin
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.section .toc,"aw",@progbits
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.LC1:
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.tc number64[TC],number64
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.data
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.globl number64
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number64:
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.quad 10
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# CHECK: Relocations [
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# The relocations in .rela.text are the 'number64' load using a
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# R_PPC64_TOC16_DS against the .toc and the 'sin' external function
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# address using a R_PPC64_REL24
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# CHECK: Section ({{[0-9]+}}) .rela.text {
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# CHECK-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_DS .toc
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# CHECK-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_REL24 sin
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# CHECK-NEXT: }
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# The .opd entry for the 'access_int64' function creates 2 relocations:
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# 1. A R_PPC64_ADDR64 against the .text segment plus addend (the function
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# address itself);
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# 2. And a R_PPC64_TOC against no symbol (the linker will replace for the
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# module's TOC base).
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# CHECK: Section ({{[0-9]+}}) .rela.opd {
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# CHECK-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_ADDR64 .text 0x0
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# CHECK-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC - 0x0
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# Finally the TOC creates the relocation for the 'number64'.
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# CHECK: Section ({{[0-9]+}}) .rela.toc {
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# CHECK-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_ADDR64 number64 0x0
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# CHECK-NEXT: }
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# CHECK-NEXT: ]
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