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https://github.com/RPCS3/llvm-mirror.git
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2bb37a1dab
Summary: This patch is the first step in reducing HW prefetcher instruction tag collisions in inner loops for Falkor. It adds a pass that annotates IR loads with metadata to indicate that they are known to be strided loads, and adds a target lowering hook that translates this metadata to a target-specific MachineMemOperand flag. A follow on change will use this MachineMemOperand flag to re-write instructions to reduce tag collisions. Reviewers: mcrosier, t.p.northover Subscribers: aemerson, rengolin, mgorny, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D34963 llvm-svn: 308059
84 lines
2.6 KiB
CMake
84 lines
2.6 KiB
CMake
set(LLVM_TARGET_DEFINITIONS AArch64.td)
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tablegen(LLVM AArch64GenRegisterInfo.inc -gen-register-info)
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tablegen(LLVM AArch64GenInstrInfo.inc -gen-instr-info)
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tablegen(LLVM AArch64GenMCCodeEmitter.inc -gen-emitter)
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tablegen(LLVM AArch64GenMCPseudoLowering.inc -gen-pseudo-lowering)
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tablegen(LLVM AArch64GenAsmWriter.inc -gen-asm-writer)
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tablegen(LLVM AArch64GenAsmWriter1.inc -gen-asm-writer -asmwriternum=1)
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tablegen(LLVM AArch64GenAsmMatcher.inc -gen-asm-matcher)
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tablegen(LLVM AArch64GenDAGISel.inc -gen-dag-isel)
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tablegen(LLVM AArch64GenFastISel.inc -gen-fast-isel)
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tablegen(LLVM AArch64GenCallingConv.inc -gen-callingconv)
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tablegen(LLVM AArch64GenSubtargetInfo.inc -gen-subtarget)
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tablegen(LLVM AArch64GenDisassemblerTables.inc -gen-disassembler)
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tablegen(LLVM AArch64GenSystemOperands.inc -gen-searchable-tables)
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if(LLVM_BUILD_GLOBAL_ISEL)
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tablegen(LLVM AArch64GenRegisterBank.inc -gen-register-bank)
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tablegen(LLVM AArch64GenGlobalISel.inc -gen-global-isel)
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endif()
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add_public_tablegen_target(AArch64CommonTableGen)
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# List of all GlobalISel files.
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set(GLOBAL_ISEL_FILES
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AArch64CallLowering.cpp
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AArch64InstructionSelector.cpp
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AArch64LegalizerInfo.cpp
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AArch64RegisterBankInfo.cpp
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)
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# Add GlobalISel files to the dependencies if the user wants to build it.
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if(LLVM_BUILD_GLOBAL_ISEL)
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set(GLOBAL_ISEL_BUILD_FILES ${GLOBAL_ISEL_FILES})
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else()
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set(GLOBAL_ISEL_BUILD_FILES"")
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set(LLVM_OPTIONAL_SOURCES LLVMGlobalISel ${GLOBAL_ISEL_FILES})
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endif()
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add_llvm_target(AArch64CodeGen
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AArch64A57FPLoadBalancing.cpp
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AArch64AdvSIMDScalarPass.cpp
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AArch64AsmPrinter.cpp
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AArch64CleanupLocalDynamicTLSPass.cpp
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AArch64CollectLOH.cpp
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AArch64CondBrTuning.cpp
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AArch64ConditionalCompares.cpp
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AArch64DeadRegisterDefinitionsPass.cpp
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AArch64ExpandPseudoInsts.cpp
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AArch64FalkorHWPFFix.cpp
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AArch64FastISel.cpp
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AArch64A53Fix835769.cpp
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AArch64FrameLowering.cpp
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AArch64ConditionOptimizer.cpp
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AArch64RedundantCopyElimination.cpp
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AArch64ISelDAGToDAG.cpp
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AArch64ISelLowering.cpp
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AArch64InstrInfo.cpp
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AArch64LoadStoreOptimizer.cpp
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AArch64MacroFusion.cpp
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AArch64MCInstLower.cpp
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AArch64PromoteConstant.cpp
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AArch64PBQPRegAlloc.cpp
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AArch64RegisterInfo.cpp
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AArch64SelectionDAGInfo.cpp
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AArch64StorePairSuppress.cpp
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AArch64Subtarget.cpp
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AArch64TargetMachine.cpp
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AArch64TargetObjectFile.cpp
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AArch64TargetTransformInfo.cpp
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AArch64VectorByElementOpt.cpp
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${GLOBAL_ISEL_BUILD_FILES}
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DEPENDS
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intrinsics_gen
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)
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add_subdirectory(TargetInfo)
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add_subdirectory(AsmParser)
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add_subdirectory(Disassembler)
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add_subdirectory(InstPrinter)
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add_subdirectory(MCTargetDesc)
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add_subdirectory(Utils)
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