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93f6871925
Summary: This is a special case for MIPS64 because the architecture requires properly 32-bit sign-extended values in the register containers. Additionaly, we merge consecutive trunc + AssertZExt nodes in order to avoid unnecessary sign-extensions when the extension comes from a type smaller than i32. Reviewers: dsanders Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D18893 llvm-svn: 266203
63 lines
2.2 KiB
LLVM
63 lines
2.2 KiB
LLVM
; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=PRE-R6
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; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=PRE-R6
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; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=PRE-R6
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; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=PRE-R6
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; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=PRE-R6
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; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=PRE-R6
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; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=R6
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; Check that we don't emit redundant SLLs for sequences of
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; (AssertZext:i32 (trunc:i32 (AssertZext:i64 X, i32)), i8)
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define zeroext i8 @udiv_i8(i8 zeroext %a, i8 zeroext %b) {
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entry:
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; ALL-LABEL: udiv_i8:
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; PRE-R6-NOT: sll {{.*}}
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; PRE-R6: divu $zero, $4, $5
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; PRE-R6: teq $5, $zero, 7
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; PRE-R6: mflo $2
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; R6-NOT: sll {{.*}}
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; R6: divu $2, $4, $5
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; R6: teq $5, $zero, 7
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%r = udiv i8 %a, %b
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ret i8 %r
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}
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; Check that we do sign-extend when we have a (trunc:i32 (AssertZext:i64 X, i32))
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define i64 @foo1(i64 zeroext %var) {
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entry:
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; ALL-LABEL: foo1:
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%shr = lshr i64 %var, 32
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%cmp = icmp eq i64 %shr, 0
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br i1 %cmp, label %if.end6, label %if.then
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; ALL: dsrl $[[T0:[0-9]+]], $4, 32
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; ALL: sll $[[T1:[0-9]+]], $[[T0]], 0
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if.then: ; preds = %entry
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%conv = trunc i64 %shr to i32
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%cmp2 = icmp slt i32 %conv, 0
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br i1 %cmp2, label %if.then4, label %if.else
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if.then4: ; preds = %if.then
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%add = add i64 %var, 16
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br label %if.end6
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if.else: ; preds = %if.then
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%add5 = add i64 %var, 32
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br label %if.end6
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if.end6: ; preds = %entry, %if.then4, %if.else
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%var.addr.0 = phi i64 [ %add, %if.then4 ], [ %add5, %if.else ], [ %var, %entry ]
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ret i64 %var.addr.0
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}
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