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https://github.com/RPCS3/llvm-mirror.git
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10839866a1
This patch implements initial backend support for a -mtune CPU controlled by a "tune-cpu" function attribute. If the attribute is not present X86 will use the resolved CPU from target-cpu attribute or command line. This patch adds MC layer support a tune CPU. Each CPU now has two sets of features stored in their GenSubtargetInfo.inc tables . These features lists are passed separately to the Processor and ProcessorModel classes in tablegen. The tune list defaults to an empty list to avoid changes to non-X86. This annoyingly increases the size of static tables on all target as we now store 24 more bytes per CPU. I haven't quantified the overall impact, but I can if we're concerned. One new test is added to X86 to show a few tuning features with mismatched tune-cpu and target-cpu/target-feature attributes to demonstrate independent control. Another new test is added to demonstrate that the scheduler model follows the tune CPU. I have not added a -mtune to llc/opt or MC layer command line yet. With no attributes we'll just use the -mcpu for both. MC layer tools will always follow the normal CPU for tuning. Differential Revision: https://reviews.llvm.org/D85165
136 lines
4.5 KiB
C++
136 lines
4.5 KiB
C++
// Add a few Bogus backend classes so we can create MachineInstrs without
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// depending on a real target.
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class BogusTargetLowering : public TargetLowering {
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public:
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BogusTargetLowering(TargetMachine &TM) : TargetLowering(TM) {}
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};
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class BogusFrameLowering : public TargetFrameLowering {
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public:
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BogusFrameLowering()
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: TargetFrameLowering(TargetFrameLowering::StackGrowsDown, Align(4), 4) {}
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void emitPrologue(MachineFunction &MF,
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MachineBasicBlock &MBB) const override {}
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void emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const override {}
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bool hasFP(const MachineFunction &MF) const override { return false; }
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};
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static TargetRegisterClass *const BogusRegisterClasses[] = {nullptr};
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class BogusRegisterInfo : public TargetRegisterInfo {
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public:
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BogusRegisterInfo()
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: TargetRegisterInfo(nullptr, BogusRegisterClasses, BogusRegisterClasses,
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nullptr, nullptr, LaneBitmask(~0u), nullptr) {
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InitMCRegisterInfo(nullptr, 0, 0, 0, nullptr, 0, nullptr, 0, nullptr,
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nullptr, nullptr, nullptr, nullptr, 0, nullptr, nullptr);
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}
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const MCPhysReg *
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getCalleeSavedRegs(const MachineFunction *MF) const override {
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return nullptr;
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}
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ArrayRef<const uint32_t *> getRegMasks() const override { return None; }
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ArrayRef<const char *> getRegMaskNames() const override { return None; }
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BitVector getReservedRegs(const MachineFunction &MF) const override {
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return BitVector();
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}
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const RegClassWeight &
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getRegClassWeight(const TargetRegisterClass *RC) const override {
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static RegClassWeight Bogus{1, 16};
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return Bogus;
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}
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unsigned getRegUnitWeight(unsigned RegUnit) const override { return 1; }
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unsigned getNumRegPressureSets() const override { return 0; }
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const char *getRegPressureSetName(unsigned Idx) const override {
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return "bogus";
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}
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unsigned getRegPressureSetLimit(const MachineFunction &MF,
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unsigned Idx) const override {
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return 0;
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}
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const int *
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getRegClassPressureSets(const TargetRegisterClass *RC) const override {
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static const int Bogus[] = {0, -1};
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return &Bogus[0];
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}
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const int *getRegUnitPressureSets(unsigned RegUnit) const override {
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static const int Bogus[] = {0, -1};
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return &Bogus[0];
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}
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Register getFrameRegister(const MachineFunction &MF) const override {
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return 0;
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}
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void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
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unsigned FIOperandNum,
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RegScavenger *RS = nullptr) const override {}
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};
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class BogusSubtarget : public TargetSubtargetInfo {
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public:
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BogusSubtarget(TargetMachine &TM)
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: TargetSubtargetInfo(Triple(""), "", "", "", {}, {}, nullptr, nullptr,
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nullptr, nullptr, nullptr, nullptr),
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FL(), TL(TM) {}
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~BogusSubtarget() override {}
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const TargetFrameLowering *getFrameLowering() const override { return &FL; }
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const TargetLowering *getTargetLowering() const override { return &TL; }
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const TargetInstrInfo *getInstrInfo() const override { return &TII; }
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const TargetRegisterInfo *getRegisterInfo() const override { return &TRI; }
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private:
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BogusFrameLowering FL;
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BogusRegisterInfo TRI;
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BogusTargetLowering TL;
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TargetInstrInfo TII;
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};
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static TargetOptions getTargetOptionsForBogusMachine() {
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TargetOptions Opts;
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Opts.EmitCallSiteInfo = true;
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return Opts;
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}
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class BogusTargetMachine : public LLVMTargetMachine {
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public:
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BogusTargetMachine()
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: LLVMTargetMachine(Target(), "", Triple(""), "", "",
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getTargetOptionsForBogusMachine(), Reloc::Static,
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CodeModel::Small, CodeGenOpt::Default),
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ST(*this) {}
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~BogusTargetMachine() override {}
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const TargetSubtargetInfo *getSubtargetImpl(const Function &) const override {
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return &ST;
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}
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private:
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BogusSubtarget ST;
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};
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std::unique_ptr<BogusTargetMachine> createTargetMachine() {
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return std::make_unique<BogusTargetMachine>();
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}
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std::unique_ptr<MachineFunction> createMachineFunction(LLVMContext &Ctx,
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Module &M) {
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auto Type = FunctionType::get(Type::getVoidTy(Ctx), false);
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auto F = Function::Create(Type, GlobalValue::ExternalLinkage, "Test", &M);
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auto TM = createTargetMachine();
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unsigned FunctionNum = 42;
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MachineModuleInfo MMI(TM.get());
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const TargetSubtargetInfo &STI = *TM->getSubtargetImpl(*F);
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return std::make_unique<MachineFunction>(*F, *TM, STI, FunctionNum, MMI);
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}
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