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b3ecd3b03e
System z branches have a mask to select which of the 4 CC values should cause the branch to be taken. We can invert a branch by inverting the mask. However, not all instructions can produce all 4 CC values, so inverting the branch like this can lead to some oddities. For example, integer comparisons only produce a CC of 0 (equal), 1 (less) or 2 (greater). If an integer EQ is reversed to NE before instruction selection, the branch will test for 1 or 2. If instead the branch is reversed after instruction selection (by inverting the mask), it will test for 1, 2 or 3. Both are correct, but the second isn't really canonical. This patch therefore keeps track of which CC values are possible and uses this when inverting a mask. Although this is mostly cosmestic, it fixes undefined behavior for the CIJNLH in branch-08.ll. Another fix would have been to mask out bit 0 when generating the fused compare and branch, but the point of this patch is that we shouldn't need to do that in the first place. The patch also makes it easier to reuse CC results from other instructions. llvm-svn: 187495
184 lines
4.9 KiB
LLVM
184 lines
4.9 KiB
LLVM
; Test 32-bit signed comparison in which the second operand is a variable.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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declare i32 @foo()
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; Check register comparison.
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define double @f1(double %a, double %b, i32 %i1, i32 %i2) {
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; CHECK-LABEL: f1:
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; CHECK: crjl %r2, %r3
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; CHECK: ldr %f0, %f2
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; CHECK: br %r14
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%cond = icmp slt i32 %i1, %i2
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%res = select i1 %cond, double %a, double %b
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ret double %res
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}
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; Check the low end of the C range.
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define double @f2(double %a, double %b, i32 %i1, i32 *%ptr) {
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; CHECK-LABEL: f2:
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; CHECK: c %r2, 0(%r3)
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; CHECK-NEXT: jl
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; CHECK: ldr %f0, %f2
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; CHECK: br %r14
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%i2 = load i32 *%ptr
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%cond = icmp slt i32 %i1, %i2
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%res = select i1 %cond, double %a, double %b
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ret double %res
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}
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; Check the high end of the aligned C range.
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define double @f3(double %a, double %b, i32 %i1, i32 *%base) {
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; CHECK-LABEL: f3:
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; CHECK: c %r2, 4092(%r3)
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; CHECK-NEXT: jl
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; CHECK: ldr %f0, %f2
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; CHECK: br %r14
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%ptr = getelementptr i32 *%base, i64 1023
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%i2 = load i32 *%ptr
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%cond = icmp slt i32 %i1, %i2
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%res = select i1 %cond, double %a, double %b
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ret double %res
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}
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; Check the next word up, which should use CY instead of C.
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define double @f4(double %a, double %b, i32 %i1, i32 *%base) {
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; CHECK-LABEL: f4:
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; CHECK: cy %r2, 4096(%r3)
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; CHECK-NEXT: jl
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; CHECK: ldr %f0, %f2
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; CHECK: br %r14
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%ptr = getelementptr i32 *%base, i64 1024
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%i2 = load i32 *%ptr
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%cond = icmp slt i32 %i1, %i2
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%res = select i1 %cond, double %a, double %b
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ret double %res
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}
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; Check the high end of the aligned CY range.
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define double @f5(double %a, double %b, i32 %i1, i32 *%base) {
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; CHECK-LABEL: f5:
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; CHECK: cy %r2, 524284(%r3)
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; CHECK-NEXT: jl
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; CHECK: ldr %f0, %f2
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; CHECK: br %r14
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%ptr = getelementptr i32 *%base, i64 131071
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%i2 = load i32 *%ptr
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%cond = icmp slt i32 %i1, %i2
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%res = select i1 %cond, double %a, double %b
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ret double %res
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}
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; Check the next word up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define double @f6(double %a, double %b, i32 %i1, i32 *%base) {
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; CHECK-LABEL: f6:
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; CHECK: agfi %r3, 524288
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; CHECK: c %r2, 0(%r3)
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; CHECK-NEXT: jl
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; CHECK: ldr %f0, %f2
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; CHECK: br %r14
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%ptr = getelementptr i32 *%base, i64 131072
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%i2 = load i32 *%ptr
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%cond = icmp slt i32 %i1, %i2
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%res = select i1 %cond, double %a, double %b
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ret double %res
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}
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; Check the high end of the negative aligned CY range.
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define double @f7(double %a, double %b, i32 %i1, i32 *%base) {
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; CHECK-LABEL: f7:
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; CHECK: cy %r2, -4(%r3)
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; CHECK-NEXT: jl
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; CHECK: ldr %f0, %f2
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; CHECK: br %r14
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%ptr = getelementptr i32 *%base, i64 -1
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%i2 = load i32 *%ptr
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%cond = icmp slt i32 %i1, %i2
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%res = select i1 %cond, double %a, double %b
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ret double %res
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}
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; Check the low end of the CY range.
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define double @f8(double %a, double %b, i32 %i1, i32 *%base) {
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; CHECK-LABEL: f8:
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; CHECK: cy %r2, -524288(%r3)
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; CHECK-NEXT: jl
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; CHECK: ldr %f0, %f2
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; CHECK: br %r14
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%ptr = getelementptr i32 *%base, i64 -131072
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%i2 = load i32 *%ptr
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%cond = icmp slt i32 %i1, %i2
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%res = select i1 %cond, double %a, double %b
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ret double %res
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}
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; Check the next word down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define double @f9(double %a, double %b, i32 %i1, i32 *%base) {
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; CHECK-LABEL: f9:
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; CHECK: agfi %r3, -524292
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; CHECK: c %r2, 0(%r3)
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; CHECK-NEXT: jl
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; CHECK: ldr %f0, %f2
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; CHECK: br %r14
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%ptr = getelementptr i32 *%base, i64 -131073
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%i2 = load i32 *%ptr
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%cond = icmp slt i32 %i1, %i2
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%res = select i1 %cond, double %a, double %b
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ret double %res
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}
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; Check that C allows an index.
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define double @f10(double %a, double %b, i32 %i1, i64 %base, i64 %index) {
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; CHECK-LABEL: f10:
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; CHECK: c %r2, 4092({{%r4,%r3|%r3,%r4}})
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; CHECK-NEXT: jl
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; CHECK: ldr %f0, %f2
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; CHECK: br %r14
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%add1 = add i64 %base, %index
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%add2 = add i64 %add1, 4092
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%ptr = inttoptr i64 %add2 to i32 *
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%i2 = load i32 *%ptr
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%cond = icmp slt i32 %i1, %i2
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%res = select i1 %cond, double %a, double %b
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ret double %res
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}
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; Check that CY allows an index.
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define double @f11(double %a, double %b, i32 %i1, i64 %base, i64 %index) {
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; CHECK-LABEL: f11:
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; CHECK: cy %r2, 4096({{%r4,%r3|%r3,%r4}})
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; CHECK-NEXT: jl
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; CHECK: ldr %f0, %f2
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; CHECK: br %r14
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%add1 = add i64 %base, %index
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%add2 = add i64 %add1, 4096
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%ptr = inttoptr i64 %add2 to i32 *
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%i2 = load i32 *%ptr
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%cond = icmp slt i32 %i1, %i2
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%res = select i1 %cond, double %a, double %b
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ret double %res
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}
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; The first branch here got recreated by InsertBranch while splitting the
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; critical edge %entry->%while.body, which lost the kills information for CC.
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define void @f12(i32 %a, i32 %b) {
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; CHECK-LABEL: f12:
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; CHECK: cije %r2, 0
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; CHECK: crjlh %r2,
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; CHECK: br %r14
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entry:
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%cmp11 = icmp eq i32 %a, 0
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br i1 %cmp11, label %while.end, label %while.body
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while.body:
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%c = call i32 @foo()
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%cmp12 = icmp eq i32 %c, %b
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br i1 %cmp12, label %while.end, label %while.body
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while.end:
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ret void
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}
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