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https://github.com/RPCS3/llvm-mirror.git
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f0a1acba8c
instructions have to distinguish between lists of single- and double-precision registers in order for the ASM matcher to do a proper job. In all other respects, a list of single- or double-precision registers are the same as a list of GPR registers. llvm-svn: 119460
220 lines
8.1 KiB
ArmAsm
220 lines
8.1 KiB
ArmAsm
@ RUN: llvm-mc -mcpu=cortex-a8 -triple armv7-apple-darwin -show-encoding < %s | FileCheck %s
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@ CHECK: vadd.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x71,0xee]
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vadd.f64 d16, d17, d16
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@ CHECK: vadd.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x30,0xee]
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vadd.f32 s0, s1, s0
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@ CHECK: vsub.f64 d16, d17, d16 @ encoding: [0xe0,0x0b,0x71,0xee]
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vsub.f64 d16, d17, d16
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@ CHECK: vsub.f32 s0, s1, s0 @ encoding: [0xc0,0x0a,0x30,0xee]
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vsub.f32 s0, s1, s0
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@ CHECK: vdiv.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0xc1,0xee]
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vdiv.f64 d16, d17, d16
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@ CHECK: vdiv.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x80,0xee]
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vdiv.f32 s0, s1, s0
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@ CHECK: vmul.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x61,0xee]
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vmul.f64 d16, d17, d16
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@ CHECK: vmul.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x20,0xee]
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vmul.f32 s0, s1, s0
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@ CHECK: vnmul.f64 d16, d17, d16 @ encoding: [0xe0,0x0b,0x61,0xee]
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vnmul.f64 d16, d17, d16
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@ CHECK: vnmul.f32 s0, s1, s0 @ encoding: [0xc0,0x0a,0x20,0xee]
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vnmul.f32 s0, s1, s0
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@ CHECK: vcmpe.f64 d17, d16 @ encoding: [0xe0,0x1b,0xf4,0xee]
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vcmpe.f64 d17, d16
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@ CHECK: vcmpe.f32 s1, s0 @ encoding: [0xc0,0x0a,0xf4,0xee]
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vcmpe.f32 s1, s0
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@ FIXME: vcmpe.f64 d16, #0 @ encoding: [0xc0,0x0b,0xf5,0xee]
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@ vcmpe.f64 d16, #0
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@ FIXME: vcmpe.f32 s0, #0 @ encoding: [0xc0,0x0a,0xb5,0xee]
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@ vcmpe.f32 s0, #0
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@ CHECK: vabs.f64 d16, d16 @ encoding: [0xe0,0x0b,0xf0,0xee]
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vabs.f64 d16, d16
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@ CHECK: vabs.f32 s0, s0 @ encoding: [0xc0,0x0a,0xb0,0xee]
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vabs.f32 s0, s0
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@ CHECK: vcvt.f32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xb7,0xee]
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vcvt.f32.f64 s0, d16
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@ CHECK: vcvt.f64.f32 d16, s0 @ encoding: [0xc0,0x0a,0xf7,0xee]
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vcvt.f64.f32 d16, s0
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@ CHECK: vneg.f64 d16, d16 @ encoding: [0x60,0x0b,0xf1,0xee]
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vneg.f64 d16, d16
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@ CHECK: vneg.f32 s0, s0 @ encoding: [0x40,0x0a,0xb1,0xee]
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vneg.f32 s0, s0
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@ CHECK: vsqrt.f64 d16, d16 @ encoding: [0xe0,0x0b,0xf1,0xee]
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vsqrt.f64 d16, d16
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@ CHECK: vsqrt.f32 s0, s0 @ encoding: [0xc0,0x0a,0xb1,0xee]
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vsqrt.f32 s0, s0
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@ CHECK: vcvt.f64.s32 d16, s0 @ encoding: [0xc0,0x0b,0xf8,0xee]
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vcvt.f64.s32 d16, s0
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@ CHECK: vcvt.f32.s32 s0, s0 @ encoding: [0xc0,0x0a,0xb8,0xee]
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vcvt.f32.s32 s0, s0
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@ CHECK: vcvt.f64.u32 d16, s0 @ encoding: [0x40,0x0b,0xf8,0xee]
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vcvt.f64.u32 d16, s0
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@ CHECK: vcvt.f32.u32 s0, s0 @ encoding: [0x40,0x0a,0xb8,0xee]
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vcvt.f32.u32 s0, s0
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@ CHECK: vcvt.s32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xbd,0xee]
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vcvt.s32.f64 s0, d16
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@ CHECK: vcvt.s32.f32 s0, s0 @ encoding: [0xc0,0x0a,0xbd,0xee]
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vcvt.s32.f32 s0, s0
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@ CHECK: vcvt.u32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xbc,0xee]
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vcvt.u32.f64 s0, d16
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@ CHECK: vcvt.u32.f32 s0, s0 @ encoding: [0xc0,0x0a,0xbc,0xee]
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vcvt.u32.f32 s0, s0
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@ CHECK: vmla.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0x42,0xee]
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vmla.f64 d16, d18, d17
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@ CHECK: vmla.f32 s1, s2, s0 @ encoding: [0x00,0x0a,0x41,0xee]
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vmla.f32 s1, s2, s0
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@ CHECK: vmls.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0x42,0xee]
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vmls.f64 d16, d18, d17
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@ CHECK: vmls.f32 s1, s2, s0 @ encoding: [0x40,0x0a,0x41,0xee]
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vmls.f32 s1, s2, s0
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@ CHECK: vnmla.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0x52,0xee]
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vnmla.f64 d16, d18, d17
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@ CHECK: vnmla.f32 s1, s2, s0 @ encoding: [0x40,0x0a,0x51,0xee]
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vnmla.f32 s1, s2, s0
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@ CHECK: vnmls.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0x52,0xee]
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vnmls.f64 d16, d18, d17
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@ CHECK: vnmls.f32 s1, s2, s0 @ encoding: [0x00,0x0a,0x51,0xee]
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vnmls.f32 s1, s2, s0
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@ FIXME: vmrs apsr_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
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@ vmrs apsr_nzcv, fpscr
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@ CHECK: vnegne.f64 d16, d16 @ encoding: [0x60,0x0b,0xf1,0x1e]
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vnegne.f64 d16, d16
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@ CHECK: vmovne s0, r0 @ encoding: [0x10,0x0a,0x00,0x1e]
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@ CHECK: vmoveq s0, r1 @ encoding: [0x10,0x1a,0x00,0x0e]
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vmovne s0, r0
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vmoveq s0, r1
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@ CHECK: vmrs r0, fpscr @ encoding: [0x10,0x0a,0xf1,0xee]
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vmrs r0, fpscr
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@ CHECK: vmsr fpscr, r0 @ encoding: [0x10,0x0a,0xe1,0xee]
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vmsr fpscr, r0
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@ FIXME: vmov.f64 d16, #3.000000e+00 @ encoding: [0x08,0x0b,0xf0,0xee]
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@ vmov.f64 d16, #3.000000e+00
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@ FIXME: vmov.f32 s0, #3.000000e+00 @ encoding: [0x08,0x0a,0xb0,0xee]
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@ vmov.f32 s0, #3.000000e+00
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@ CHECK: vmov s0, r0 @ encoding: [0x10,0x0a,0x00,0xee]
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@ CHECK: vmov s1, r1 @ encoding: [0x90,0x1a,0x00,0xee]
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@ CHECK: vmov s2, r2 @ encoding: [0x10,0x2a,0x01,0xee]
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@ CHECK: vmov s3, r3 @ encoding: [0x90,0x3a,0x01,0xee]
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vmov s0, r0
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vmov s1, r1
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vmov s2, r2
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vmov s3, r3
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@ CHECK: vmov r0, s0 @ encoding: [0x10,0x0a,0x10,0xee]
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@ CHECK: vmov r1, s1 @ encoding: [0x90,0x1a,0x10,0xee]
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@ CHECK: vmov r2, s2 @ encoding: [0x10,0x2a,0x11,0xee]
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@ CHECK: vmov r3, s3 @ encoding: [0x90,0x3a,0x11,0xee]
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vmov r0, s0
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vmov r1, s1
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vmov r2, s2
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vmov r3, s3
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@ CHECK: vmov r0, r1, d16 @ encoding: [0x30,0x0b,0x51,0xec]
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vmov r0, r1, d16
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@ CHECK: vldr.64 d17, [r0] @ encoding: [0x00,0x1b,0xd0,0xed]
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vldr.64 d17, [r0]
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@ CHECK: vldr.64 d1, [r2, #32] @ encoding: [0x08,0x1b,0x92,0xed]
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@ CHECK: vldr.64 d1, [r2, #-32] @ encoding: [0x08,0x1b,0x12,0xed]
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vldr.64 d1, [r2, #32]
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vldr.64 d1, [r2, #-32]
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@ CHECK: vldr.64 d2, [r3] @ encoding: [0x00,0x2b,0x93,0xed]
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vldr.64 d2, [r3]
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@ CHECK: vldr.64 d3, [pc] @ encoding: [0x00,0x3b,0x9f,0xed]
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@ CHECK: vldr.64 d3, [pc] @ encoding: [0x00,0x3b,0x9f,0xed]
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@ CHECK: vldr.64 d3, [pc] @ encoding: [0x00,0x3b,0x9f,0xed]
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vldr.64 d3, [pc]
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vldr.64 d3, [pc,#0]
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vldr.64 d3, [pc,#-0]
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@ CHECK: vldr.32 s13, [r0] @ encoding: [0x00,0x6a,0xd0,0xed]
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vldr.32 s13, [r0]
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@ CHECK: vldr.32 s1, [r2, #32] @ encoding: [0x08,0x0a,0xd2,0xed]
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@ CHECK: vldr.32 s1, [r2, #-32] @ encoding: [0x08,0x0a,0x52,0xed]
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vldr.32 s1, [r2, #32]
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vldr.32 s1, [r2, #-32]
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@ CHECK: vldr.32 s2, [r3] @ encoding: [0x00,0x1a,0x93,0xed]
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vldr.32 s2, [r3]
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@ CHECK: vldr.32 s5, [pc] @ encoding: [0x00,0x2a,0xdf,0xed]
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@ CHECK: vldr.32 s5, [pc] @ encoding: [0x00,0x2a,0xdf,0xed]
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@ CHECK: vldr.32 s5, [pc] @ encoding: [0x00,0x2a,0xdf,0xed]
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vldr.32 s5, [pc]
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vldr.32 s5, [pc,#0]
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vldr.32 s5, [pc,#-0]
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@ CHECK: vstr.64 d4, [r1] @ encoding: [0x00,0x4b,0x81,0xed]
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@ CHECK: vstr.64 d4, [r1, #24] @ encoding: [0x06,0x4b,0x81,0xed]
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@ CHECK: vstr.64 d4, [r1, #-24] @ encoding: [0x06,0x4b,0x01,0xed]
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vstr.64 d4, [r1]
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vstr.64 d4, [r1, #24]
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vstr.64 d4, [r1, #-24]
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@ CHECK: vstr.32 s4, [r1] @ encoding: [0x00,0x2a,0x81,0xed]
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@ CHECK: vstr.32 s4, [r1, #24] @ encoding: [0x06,0x2a,0x81,0xed]
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@ CHECK: vstr.32 s4, [r1, #-24] @ encoding: [0x06,0x2a,0x01,0xed]
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vstr.32 s4, [r1]
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vstr.32 s4, [r1, #24]
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vstr.32 s4, [r1, #-24]
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@ CHECK: vldmia r1, {d2, d3, d4, d5, d6, d7} @ encoding: [0x0c,0x2b,0x91,0xec]
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@ CHECK: vldmia r1, {s2, s3, s4, s5, s6, s7} @ encoding: [0x06,0x1a,0x91,0xec]
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vldmia r1, {d2,d3-d6,d7}
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vldmia r1, {s2,s3-s6,s7}
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@ CHECK: vstmia r1, {d2, d3, d4, d5, d6, d7} @ encoding: [0x0c,0x2b,0x81,0xec]
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@ CHECK: vstmia r1, {s2, s3, s4, s5, s6, s7} @ encoding: [0x06,0x1a,0x81,0xec]
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vstmia r1, {d2,d3-d6,d7}
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vstmia r1, {s2,s3-s6,s7}
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