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cbce5f6883
This patch adds support for: UZP1 Concatenate even elements from two vectors UZP2 Concatenate odd elements from two vectors TRN1 Interleave even elements from two vectors TRN2 Interleave odd elements from two vectors With variants for both data and predicate vectors, e.g. uzp1 z0.b, z1.b, z2.b trn2 p0.s, p1.s, p2.s llvm-svn: 336531
44 lines
1.5 KiB
ArmAsm
44 lines
1.5 KiB
ArmAsm
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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// Invalid element kind.
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uzp1 z10.h, z22.h, z31.x
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid vector kind qualifier
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// CHECK-NEXT: uzp1 z10.h, z22.h, z31.x
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// Element size specifiers should match.
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uzp1 z10.h, z3.h, z15.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: uzp1 z10.h, z3.h, z15.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// Too few operands
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uzp1 z1.h, z2.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: too few operands for instruction
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// CHECK-NEXT: uzp1 z1.h, z2.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// z32 is not a valid SVE data register
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uzp1 z1.s, z2.s, z32.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: uzp1 z1.s, z2.s, z32.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// p16 is not a valid SVE predicate register
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uzp1 p1.s, p2.s, p16.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: uzp1 p1.s, p2.s, p16.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// Combining data and predicate registers as operands
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uzp1 z1.s, z2.s, p3.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: uzp1 z1.s, z2.s, p3.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// Combining predicate and data registers as operands
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uzp1 p1.s, p2.s, z3.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: uzp1 p1.s, p2.s, z3.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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