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89371f799d
This patch adds addsub_imm8_opt_lsl_(i8|i16|i32|i64) operands that are unsigned values in the range 0 to 255. For element widths of 16 bits or higher it may also be a signed multiple of 256 in the range 0 to 65280. Note: This also does some refactoring to reuse convenience function getShiftedVal<shift>(), and now allows AArch64 scalar 'ADD #-4096' to be accepted to be mapped to SUB #4096. Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D47310 llvm-svn: 333408
126 lines
4.2 KiB
ArmAsm
126 lines
4.2 KiB
ArmAsm
// RUN: llvm-mc -triple=aarch64-none-linux-gnu < %s | FileCheck %s
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// RUN: not llvm-mc -mattr=+no-neg-immediates -triple=aarch64-none-linux-gnu < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-NEG-IMM
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add w0, w2, #4096
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sub w0, w2, #4096
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// CHECK: add w0, w2, #1, lsl #12
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// CHECK: sub w0, w2, #1, lsl #12
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add w0, w2, #-4096
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sub w0, w2, #-4096
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// CHECK: sub w0, w2, #1, lsl #12
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// CHECK: add w0, w2, #1, lsl #12
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// CHECK: sub w0, w2, #2, lsl #12
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// CHECK: sub w0, w2, #2, lsl #12
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// CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
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sub w0, w2, #2, lsl 12
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add w0, w2, #-2, lsl 12
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// CHECK: sub x1, x3, #2, lsl #12
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// CHECK: sub x1, x3, #2, lsl #12
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// CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
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sub x1, x3, #2, lsl 12
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add x1, x3, #-2, lsl 12
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// CHECK: sub x1, x3, #4
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// CHECK: sub x1, x3, #4
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// CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
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sub x1, x3, #4
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add x1, x3, #-4
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// CHECK: sub x1, x3, #4095
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// CHECK: sub x1, x3, #4095
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// CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
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sub x1, x3, #4095, lsl 0
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add x1, x3, #-4095, lsl 0
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// CHECK: sub x3, x4, #0
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sub x3, x4, #0
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// CHECK: add w0, w2, #2, lsl #12
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// CHECK: add w0, w2, #2, lsl #12
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// CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
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add w0, w2, #2, lsl 12
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sub w0, w2, #-2, lsl 12
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// CHECK: add x1, x3, #2, lsl #12
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// CHECK: add x1, x3, #2, lsl #12
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// CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
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add x1, x3, #2, lsl 12
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sub x1, x3, #-2, lsl 12
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// CHECK: add x1, x3, #4
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// CHECK: add x1, x3, #4
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// CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
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add x1, x3, #4
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sub x1, x3, #-4
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// CHECK: add x1, x3, #4095
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// CHECK: add x1, x3, #4095
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// CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
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add x1, x3, #4095, lsl 0
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sub x1, x3, #-4095, lsl 0
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// CHECK: add x2, x5, #0
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add x2, x5, #0
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// CHECK: subs w0, w2, #2, lsl #12
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// CHECK: subs w0, w2, #2, lsl #12
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// CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
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subs w0, w2, #2, lsl 12
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adds w0, w2, #-2, lsl 12
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// CHECK: subs x1, x3, #2, lsl #12
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// CHECK: subs x1, x3, #2, lsl #12
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// CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
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subs x1, x3, #2, lsl 12
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adds x1, x3, #-2, lsl 12
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// CHECK: subs x1, x3, #4
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// CHECK: subs x1, x3, #4
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// CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
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subs x1, x3, #4
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adds x1, x3, #-4
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// CHECK: subs x1, x3, #4095
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// CHECK: subs x1, x3, #4095
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// CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
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subs x1, x3, #4095, lsl 0
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adds x1, x3, #-4095, lsl 0
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// CHECK: subs x3, x4, #0
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subs x3, x4, #0
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// CHECK: adds w0, w2, #2, lsl #12
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// CHECK: adds w0, w2, #2, lsl #12
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// CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
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adds w0, w2, #2, lsl 12
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subs w0, w2, #-2, lsl 12
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// CHECK: adds x1, x3, #2, lsl #12
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// CHECK: adds x1, x3, #2, lsl #12
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// CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
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adds x1, x3, #2, lsl 12
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subs x1, x3, #-2, lsl 12
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// CHECK: adds x1, x3, #4
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// CHECK: adds x1, x3, #4
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// CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
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adds x1, x3, #4
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subs x1, x3, #-4
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// CHECK: adds x1, x3, #4095
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// CHECK: adds x1, x3, #4095
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// CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
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adds x1, x3, #4095, lsl 0
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subs x1, x3, #-4095, lsl 0
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// CHECK: adds x2, x5, #0
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adds x2, x5, #0
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// CHECK: {{adds xzr,|cmn}} x5, #5
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// CHECK: {{adds xzr,|cmn}} x5, #5
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// CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
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cmn x5, #5
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cmp x5, #-5
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// CHECK: {{subs xzr,|cmp}} x6, #4095
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// CHECK: {{subs xzr,|cmp}} x6, #4095
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// CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
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cmp x6, #4095
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cmn x6, #-4095
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// CHECK: {{adds wzr,|cmn}} w7, #5
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// CHECK: {{adds wzr,|cmn}} w7, #5
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// CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
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cmn w7, #5
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cmp w7, #-5
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// CHECK: {{subs wzr,|cmp}} w8, #4095
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// CHECK: {{subs wzr,|cmp}} w8, #4095
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// CHECK-NO-NEG-IMM: instruction requires: NegativeImmediates
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cmp w8, #4095
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cmn w8, #-4095
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