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6958800987
TableGen checks at compiletime that for scheduling models with
"CompleteModel = 1" one of the following holds:
- Is marked with the hasNoSchedulingInfo flag
- The instruction is a subclass of Sched
- There are InstRW definitions in the scheduling model
Typical steps necessary to complete a model:
- Ensure all pseudo instructions that are expanded before machine
scheduling (usually everything handled with EmitYYY() functions in
XXXTargetLowering).
- If a CPU does not support some instructions mark the corresponding
resource unsupported: "WriteRes<WriteXXX, []> { let Unsupported = 1; }".
- Add missing scheduling information.
Differential Revision: http://reviews.llvm.org/D17747
llvm-svn: 262384
172 lines
8.5 KiB
TableGen
172 lines
8.5 KiB
TableGen
//=-HexagonScheduleV4.td - HexagonV4 Scheduling Definitions --*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// There are four SLOTS (four parallel pipelines) in Hexagon V4 machine.
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// This file describes that machine information.
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//
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// |===========|==================================================|
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// | PIPELINE | Instruction Classes |
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// |===========|==================================================|
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// | SLOT0 | LD ST ALU32 MEMOP NV SYSTEM |
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// |-----------|--------------------------------------------------|
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// | SLOT1 | LD ST ALU32 |
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// |-----------|--------------------------------------------------|
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// | SLOT2 | XTYPE ALU32 J JR |
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// |-----------|--------------------------------------------------|
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// | SLOT3 | XTYPE ALU32 J CR |
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// |===========|==================================================|
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def CJ_tc_1_SLOT23 : InstrItinClass;
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def CJ_tc_2early_SLOT23 : InstrItinClass;
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def COPROC_VMEM_vtc_long_SLOT01 : InstrItinClass;
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def COPROC_VX_vtc_long_SLOT23 : InstrItinClass;
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def COPROC_VX_vtc_SLOT23 : InstrItinClass;
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def J_tc_3stall_SLOT2 : InstrItinClass;
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def MAPPING_tc_1_SLOT0123 : InstrItinClass;
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def M_tc_3stall_SLOT23 : InstrItinClass;
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def SUBINSN_tc_1_SLOT01 : InstrItinClass;
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def SUBINSN_tc_2early_SLOT0 : InstrItinClass;
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def SUBINSN_tc_2early_SLOT01 : InstrItinClass;
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def SUBINSN_tc_3stall_SLOT0 : InstrItinClass;
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def SUBINSN_tc_ld_SLOT0 : InstrItinClass;
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def SUBINSN_tc_ld_SLOT01 : InstrItinClass;
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def SUBINSN_tc_st_SLOT01 : InstrItinClass;
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def HexagonItinerariesV55 :
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ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP], [], [
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// ALU32
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InstrItinData<ALU32_2op_tc_1_SLOT0123 ,
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[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
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InstrItinData<ALU32_2op_tc_2early_SLOT0123,
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[InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
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InstrItinData<ALU32_3op_tc_1_SLOT0123 ,
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[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
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InstrItinData<ALU32_3op_tc_2_SLOT0123 ,
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[InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
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InstrItinData<ALU32_3op_tc_2early_SLOT0123,
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[InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
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InstrItinData<ALU32_ADDI_tc_1_SLOT0123 ,
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[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
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// ALU64
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InstrItinData<ALU64_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
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InstrItinData<ALU64_tc_2_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>,
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InstrItinData<ALU64_tc_2early_SLOT23, [InstrStage<2, [SLOT2, SLOT3]>]>,
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InstrItinData<ALU64_tc_3x_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>,
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// CR -> System
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InstrItinData<CR_tc_2_SLOT3 , [InstrStage<2, [SLOT3]>]>,
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InstrItinData<CR_tc_2early_SLOT3 , [InstrStage<2, [SLOT3]>]>,
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InstrItinData<CR_tc_3x_SLOT3 , [InstrStage<3, [SLOT3]>]>,
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// Jump (conditional/unconditional/return etc)
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InstrItinData<CR_tc_2early_SLOT23, [InstrStage<2, [SLOT2, SLOT3]>]>,
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InstrItinData<CR_tc_3x_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>,
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InstrItinData<CJ_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
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InstrItinData<CJ_tc_2early_SLOT23, [InstrStage<2, [SLOT2, SLOT3]>]>,
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InstrItinData<J_tc_2early_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>,
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InstrItinData<J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT , [InstrStage<1, [SLOT2, SLOT3]>]>,
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// JR
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InstrItinData<J_tc_2early_SLOT2 , [InstrStage<2, [SLOT2]>]>,
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InstrItinData<J_tc_3stall_SLOT2 , [InstrStage<3, [SLOT2]>]>,
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// Extender
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InstrItinData<EXTENDER_tc_1_SLOT0123,
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[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
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// Load
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InstrItinData<LD_tc_ld_SLOT01 , [InstrStage<3, [SLOT0, SLOT1]>]>,
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InstrItinData<LD_tc_3or4stall_SLOT0, [InstrStage<3, [SLOT0]>]>,
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InstrItinData<LD_tc_ld_SLOT0 , [InstrStage<3, [SLOT0]>]>,
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// M
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InstrItinData<M_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
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InstrItinData<M_tc_2_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>,
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InstrItinData<M_tc_3_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>,
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InstrItinData<M_tc_3x_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>,
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InstrItinData<M_tc_3or4x_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>,
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InstrItinData<M_tc_3stall_SLOT23, [InstrStage<3, [SLOT2, SLOT3]>]>,
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// Store
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InstrItinData<ST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
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InstrItinData<ST_tc_3stall_SLOT0, [InstrStage<3, [SLOT0]>]>,
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InstrItinData<ST_tc_ld_SLOT0 , [InstrStage<3, [SLOT0]>]>,
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InstrItinData<ST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>]>,
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// Subinsn
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InstrItinData<SUBINSN_tc_2early_SLOT0, [InstrStage<2, [SLOT0]>]>,
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InstrItinData<SUBINSN_tc_3stall_SLOT0, [InstrStage<3, [SLOT0]>]>,
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InstrItinData<SUBINSN_tc_ld_SLOT0 , [InstrStage<3, [SLOT0]>]>,
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InstrItinData<SUBINSN_tc_1_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
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InstrItinData<SUBINSN_tc_2early_SLOT01,
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[InstrStage<2, [SLOT0, SLOT1]>]>,
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InstrItinData<SUBINSN_tc_ld_SLOT01 , [InstrStage<3, [SLOT0, SLOT1]>]>,
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InstrItinData<SUBINSN_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
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// S
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InstrItinData<S_2op_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
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InstrItinData<S_2op_tc_2_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>,
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InstrItinData<S_2op_tc_2early_SLOT23, [InstrStage<2, [SLOT2, SLOT3]>]>,
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InstrItinData<S_2op_tc_3or4x_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>,
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InstrItinData<S_3op_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
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InstrItinData<S_3op_tc_2_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>,
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InstrItinData<S_3op_tc_2early_SLOT23, [InstrStage<2, [SLOT2, SLOT3]>]>,
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InstrItinData<S_3op_tc_3_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>,
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InstrItinData<S_3op_tc_3stall_SLOT23, [InstrStage<3, [SLOT2, SLOT3]>]>,
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InstrItinData<S_3op_tc_3x_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>,
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// New Value Compare Jump
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InstrItinData<NCJ_tc_3or4stall_SLOT0, [InstrStage<3, [SLOT0]>]>,
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// Mem ops
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InstrItinData<V2LDST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>]>,
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InstrItinData<V2LDST_tc_ld_SLOT01 , [InstrStage<2, [SLOT0, SLOT1]>]>,
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InstrItinData<V2LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
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InstrItinData<V4LDST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>]>,
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InstrItinData<V4LDST_tc_ld_SLOT01 , [InstrStage<3, [SLOT0, SLOT1]>]>,
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InstrItinData<V4LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
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// Endloop
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InstrItinData<J_tc_2early_SLOT0123, [InstrStage<2, [SLOT_ENDLOOP]>]>,
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// Vector
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InstrItinData<COPROC_VMEM_vtc_long_SLOT01,
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[InstrStage<3, [SLOT0, SLOT1]>]>,
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InstrItinData<COPROC_VX_vtc_long_SLOT23 ,
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[InstrStage<3, [SLOT2, SLOT3]>]>,
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InstrItinData<COPROC_VX_vtc_SLOT23 ,
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[InstrStage<3, [SLOT2, SLOT3]>]>,
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InstrItinData<MAPPING_tc_1_SLOT0123 ,
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[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
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// Misc
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InstrItinData<COMPOUND_CJ_ARCHDEPSLOT , [InstrStage<1, [SLOT2, SLOT3]>]>,
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InstrItinData<COMPOUND , [InstrStage<1, [SLOT2, SLOT3]>]>,
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InstrItinData<DUPLEX , [InstrStage<1, [SLOT0]>]>,
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InstrItinData<PREFIX , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
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InstrItinData<PSEUDO , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
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InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
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InstrStage<1, [SLOT2, SLOT3]>]>
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]>;
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def HexagonModelV55 : SchedMachineModel {
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// Max issue per cycle == bundle width.
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let IssueWidth = 4;
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let Itineraries = HexagonItinerariesV55;
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let LoadLatency = 1;
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let CompleteModel = 0;
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}
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//===----------------------------------------------------------------------===//
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// Hexagon V4 Resource Definitions -
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//===----------------------------------------------------------------------===//
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