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6958800987
TableGen checks at compiletime that for scheduling models with
"CompleteModel = 1" one of the following holds:
- Is marked with the hasNoSchedulingInfo flag
- The instruction is a subclass of Sched
- There are InstRW definitions in the scheduling model
Typical steps necessary to complete a model:
- Ensure all pseudo instructions that are expanded before machine
scheduling (usually everything handled with EmitYYY() functions in
XXXTargetLowering).
- If a CPU does not support some instructions mark the corresponding
resource unsupported: "WriteRes<WriteXXX, []> { let Unsupported = 1; }".
- Add missing scheduling information.
Differential Revision: http://reviews.llvm.org/D17747
llvm-svn: 262384
312 lines
16 KiB
TableGen
312 lines
16 KiB
TableGen
//=-HexagonScheduleV60.td - HexagonV60 Scheduling Definitions *- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// CVI pipes from the "Hexagon Multimedia Co-Processor Extensions Arch Spec".
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def CVI_ST : FuncUnit;
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def CVI_XLANE : FuncUnit;
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def CVI_SHIFT : FuncUnit;
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def CVI_MPY0 : FuncUnit;
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def CVI_MPY1 : FuncUnit;
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def CVI_LD : FuncUnit;
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// Combined functional units.
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def CVI_XLSHF : FuncUnit;
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def CVI_MPY01 : FuncUnit;
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def CVI_ALL : FuncUnit;
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// Combined functional unit data.
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def HexagonComboFuncsV60 :
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ComboFuncUnits<[
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ComboFuncData<CVI_XLSHF , [CVI_XLANE, CVI_SHIFT]>,
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ComboFuncData<CVI_MPY01 , [CVI_MPY0, CVI_MPY1]>,
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ComboFuncData<CVI_ALL , [CVI_ST, CVI_XLANE, CVI_SHIFT,
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CVI_MPY0, CVI_MPY1, CVI_LD]>
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]>;
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// Note: When adding additional vector scheduling classes, add the
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// corresponding methods to the class HexagonInstrInfo.
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def CVI_VA : InstrItinClass;
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def CVI_VA_DV : InstrItinClass;
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def CVI_VX_LONG : InstrItinClass;
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def CVI_VX_LATE : InstrItinClass;
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def CVI_VX : InstrItinClass;
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def CVI_VX_DV_LONG : InstrItinClass;
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def CVI_VX_DV : InstrItinClass;
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def CVI_VX_DV_SLOT2 : InstrItinClass;
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def CVI_VP : InstrItinClass;
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def CVI_VP_LONG : InstrItinClass;
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def CVI_VP_VS_EARLY : InstrItinClass;
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def CVI_VP_VS_LONG_EARLY : InstrItinClass;
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def CVI_VP_VS_LONG : InstrItinClass;
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def CVI_VP_VS : InstrItinClass;
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def CVI_VP_DV : InstrItinClass;
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def CVI_VS : InstrItinClass;
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def CVI_VINLANESAT : InstrItinClass;
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def CVI_VM_LD : InstrItinClass;
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def CVI_VM_TMP_LD : InstrItinClass;
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def CVI_VM_CUR_LD : InstrItinClass;
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def CVI_VM_VP_LDU : InstrItinClass;
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def CVI_VM_ST : InstrItinClass;
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def CVI_VM_NEW_ST : InstrItinClass;
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def CVI_VM_STU : InstrItinClass;
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def CVI_HIST : InstrItinClass;
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def CVI_VA_EXT : InstrItinClass;
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// There are four SLOTS (four parallel pipelines) in Hexagon V60 machine.
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// This file describes that machine information.
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//
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// |===========|==================================================|
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// | PIPELINE | Instruction Classes |
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// |===========|==================================================|
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// | SLOT0 | LD ST ALU32 MEMOP NV SYSTEM |
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// |-----------|--------------------------------------------------|
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// | SLOT1 | LD ST ALU32 |
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// |-----------|--------------------------------------------------|
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// | SLOT2 | XTYPE ALU32 J JR |
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// |-----------|--------------------------------------------------|
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// | SLOT3 | XTYPE ALU32 J CR |
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// |===========|==================================================|
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//
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//
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// In addition to using the above SLOTS, there are also six vector pipelines
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// in the CVI co-processor in the Hexagon V60 machine.
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//
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// |=========| |=========| |=========| |=========| |=========| |=========|
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// SLOT | CVI_LD | |CVI_MPY3 | |CVI_MPY2 | |CVI_SHIFT| |CVI_XLANE| | CVI_ST |
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// ==== |=========| |=========| |=========| |=========| |=========| |=========|
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// S0-3 | | | CVI_VA | | CVI_VA | | CVI_VA | | CVI_VA | | |
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// S2-3 | | | CVI_VX | | CVI_VX | | | | | | |
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// S0-3 | | | | | | | | | CVI_VP | | |
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// S0-3 | | | | | | | CVI_VS | | | | |
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// S0-1 |(CVI_LD) | | CVI_LD | | CVI_LD | | CVI_LD | | CVI_LD | | |
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// S0-1 |(C*TMP_LD) | | | | | | | | | |
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// S01 |(C*_LDU) | | | | | | | | C*_LDU | | |
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// S0 | | | CVI_ST | | CVI_ST | | CVI_ST | | CVI_ST | |(CVI_ST) |
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// S0 | | | | | | | | | | |(C*TMP_ST)
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// S01 | | | | | | | | | VSTU | |(C*_STU) |
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// |=========| |=========| |=========| |=========| |=========| |=========|
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// |=====================| |=====================|
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// | CVI_MPY2 & CVI_MPY3 | |CVI_XLANE & CVI_SHIFT|
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// |=====================| |=====================|
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// S0-3 | CVI_VA_DV | | CVI_VA_DV |
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// S0-3 | | | CVI_VP_DV |
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// S2-3 | CVI_VX_DV | | |
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// |=====================| |=====================|
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// |=====================================================================|
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// S0-3 | CVI_HIST Histogram |
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// S0123| CVI_VA_EXT Extract |
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// |=====================================================================|
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def HexagonItinerariesV60 :
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ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
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CVI_ST, CVI_XLANE, CVI_SHIFT, CVI_MPY0, CVI_MPY1,
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CVI_LD, CVI_XLSHF, CVI_MPY01, CVI_ALL], [], [
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// ALU32
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InstrItinData<ALU32_2op_tc_1_SLOT0123 ,
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[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
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InstrItinData<ALU32_2op_tc_2early_SLOT0123,
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[InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
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InstrItinData<ALU32_3op_tc_1_SLOT0123 ,
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[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
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InstrItinData<ALU32_3op_tc_2_SLOT0123 ,
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[InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
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InstrItinData<ALU32_3op_tc_2early_SLOT0123,
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[InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
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InstrItinData<ALU32_ADDI_tc_1_SLOT0123 ,
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[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
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// ALU64
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InstrItinData<ALU64_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
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InstrItinData<ALU64_tc_2_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>,
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InstrItinData<ALU64_tc_2early_SLOT23, [InstrStage<2, [SLOT2, SLOT3]>]>,
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InstrItinData<ALU64_tc_3x_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>,
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// CR -> System
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InstrItinData<CR_tc_2_SLOT3 , [InstrStage<2, [SLOT3]>]>,
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InstrItinData<CR_tc_2early_SLOT3 , [InstrStage<2, [SLOT3]>]>,
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InstrItinData<CR_tc_3x_SLOT3 , [InstrStage<3, [SLOT3]>]>,
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// Jump (conditional/unconditional/return etc)
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InstrItinData<CR_tc_2early_SLOT23, [InstrStage<2, [SLOT2, SLOT3]>]>,
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InstrItinData<CR_tc_3x_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>,
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InstrItinData<CJ_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
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InstrItinData<CJ_tc_2early_SLOT23, [InstrStage<2, [SLOT2, SLOT3]>]>,
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InstrItinData<J_tc_2early_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>,
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InstrItinData<J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT , [InstrStage<1, [SLOT2, SLOT3]>]>,
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// JR
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InstrItinData<J_tc_2early_SLOT2 , [InstrStage<2, [SLOT2]>]>,
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InstrItinData<J_tc_3stall_SLOT2 , [InstrStage<3, [SLOT2]>]>,
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// Extender
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InstrItinData<EXTENDER_tc_1_SLOT0123, [InstrStage<1,
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[SLOT0, SLOT1, SLOT2, SLOT3]>]>,
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// Load
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InstrItinData<LD_tc_ld_SLOT01 , [InstrStage<3, [SLOT0, SLOT1]>]>,
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InstrItinData<LD_tc_3or4stall_SLOT0, [InstrStage<4, [SLOT0]>]>,
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InstrItinData<LD_tc_ld_SLOT0 , [InstrStage<3, [SLOT0]>]>,
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// M
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InstrItinData<M_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
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InstrItinData<M_tc_2_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>,
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InstrItinData<M_tc_3_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>,
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InstrItinData<M_tc_3x_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>,
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InstrItinData<M_tc_3or4x_SLOT23 , [InstrStage<4, [SLOT2, SLOT3]>]>,
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InstrItinData<M_tc_3stall_SLOT23, [InstrStage<3, [SLOT2, SLOT3]>]>,
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// Store
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InstrItinData<ST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
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InstrItinData<ST_tc_3stall_SLOT0, [InstrStage<3, [SLOT0]>]>,
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InstrItinData<ST_tc_ld_SLOT0 , [InstrStage<3, [SLOT0]>]>,
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InstrItinData<ST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>]>,
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// Subinsn
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InstrItinData<SUBINSN_tc_2early_SLOT0, [InstrStage<2, [SLOT0]>]>,
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InstrItinData<SUBINSN_tc_3stall_SLOT0, [InstrStage<3, [SLOT0]>]>,
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InstrItinData<SUBINSN_tc_ld_SLOT0 , [InstrStage<3, [SLOT0]>]>,
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InstrItinData<SUBINSN_tc_1_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
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InstrItinData<SUBINSN_tc_2early_SLOT01,
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[InstrStage<2, [SLOT0, SLOT1]>]>,
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InstrItinData<SUBINSN_tc_ld_SLOT01 , [InstrStage<3, [SLOT0, SLOT1]>]>,
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InstrItinData<SUBINSN_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
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// S
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InstrItinData<S_2op_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
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InstrItinData<S_2op_tc_2_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>,
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InstrItinData<S_2op_tc_2early_SLOT23, [InstrStage<2, [SLOT2, SLOT3]>]>,
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// The S_2op_tc_3x_SLOT23 slots are 4 cycles on v60.
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InstrItinData<S_2op_tc_3or4x_SLOT23 , [InstrStage<4, [SLOT2, SLOT3]>]>,
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InstrItinData<S_3op_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
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InstrItinData<S_3op_tc_2_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>,
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InstrItinData<S_3op_tc_2early_SLOT23, [InstrStage<2, [SLOT2, SLOT3]>]>,
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InstrItinData<S_3op_tc_3_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>,
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InstrItinData<S_3op_tc_3stall_SLOT23, [InstrStage<3, [SLOT2, SLOT3]>]>,
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InstrItinData<S_3op_tc_3x_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>,
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// New Value Compare Jump
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InstrItinData<NCJ_tc_3or4stall_SLOT0, [InstrStage<4, [SLOT0]>]>,
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// Mem ops
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InstrItinData<V2LDST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>]>,
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InstrItinData<V2LDST_tc_ld_SLOT01 , [InstrStage<2, [SLOT0, SLOT1]>]>,
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InstrItinData<V2LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
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InstrItinData<V4LDST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>]>,
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InstrItinData<V4LDST_tc_ld_SLOT01 , [InstrStage<3, [SLOT0, SLOT1]>]>,
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InstrItinData<V4LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
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// Endloop
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InstrItinData<J_tc_2early_SLOT0123, [InstrStage<2, [SLOT_ENDLOOP]>]>,
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// Vector
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InstrItinData<COPROC_VMEM_vtc_long_SLOT01,
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[InstrStage<3, [SLOT0, SLOT1]>]>,
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InstrItinData<COPROC_VX_vtc_long_SLOT23 ,
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[InstrStage<3, [SLOT2, SLOT3]>]>,
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InstrItinData<COPROC_VX_vtc_SLOT23 ,
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[InstrStage<3, [SLOT2, SLOT3]>]>,
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InstrItinData<MAPPING_tc_1_SLOT0123 ,
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[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
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// Duplex and Compound
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InstrItinData<DUPLEX , [InstrStage<1, [SLOT0]>]>,
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InstrItinData<COMPOUND_CJ_ARCHDEPSLOT , [InstrStage<1, [SLOT2, SLOT3]>]>,
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InstrItinData<COMPOUND , [InstrStage<1, [SLOT2, SLOT3]>]>,
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// Misc
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InstrItinData<PREFIX , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
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InstrItinData<PSEUDO , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
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InstrItinData<PSEUDOM , [InstrStage<1, [SLOT2, SLOT3], 0>,
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InstrStage<1, [SLOT2, SLOT3]>]>,
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// Latest CVI spec definitions.
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InstrItinData<CVI_VA,[InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
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InstrStage<1, [CVI_XLANE,CVI_SHIFT,
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CVI_MPY0, CVI_MPY1]>]>,
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InstrItinData<CVI_VA_DV,
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[InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
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InstrStage<1, [CVI_XLSHF, CVI_MPY01]>]>,
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InstrItinData<CVI_VX_LONG, [InstrStage<1, [SLOT2, SLOT3], 0>,
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InstrStage<1, [CVI_MPY0, CVI_MPY1]>]>,
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InstrItinData<CVI_VX_LATE, [InstrStage<1, [SLOT2, SLOT3], 0>,
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InstrStage<1, [CVI_MPY0, CVI_MPY1]>]>,
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InstrItinData<CVI_VX,[InstrStage<1, [SLOT2, SLOT3], 0>,
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InstrStage<1, [CVI_MPY0, CVI_MPY1]>]>,
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InstrItinData<CVI_VX_DV_LONG,
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[InstrStage<1, [SLOT2, SLOT3], 0>,
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InstrStage<1, [CVI_MPY01]>]>,
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InstrItinData<CVI_VX_DV,
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[InstrStage<1, [SLOT2, SLOT3], 0>,
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InstrStage<1, [CVI_MPY01]>]>,
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InstrItinData<CVI_VX_DV_SLOT2,
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[InstrStage<1, [SLOT2], 0>,
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InstrStage<1, [CVI_MPY01]>]>,
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InstrItinData<CVI_VP, [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
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InstrStage<1, [CVI_XLANE]>]>,
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InstrItinData<CVI_VP_LONG, [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
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InstrStage<1, [CVI_XLANE]>]>,
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InstrItinData<CVI_VP_VS_EARLY,
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[InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
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InstrStage<1, [CVI_XLSHF]>]>,
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InstrItinData<CVI_VP_VS_LONG,
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[InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
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InstrStage<1, [CVI_XLSHF]>]>,
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InstrItinData<CVI_VP_VS,
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[InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
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InstrStage<1, [CVI_XLSHF]>]>,
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InstrItinData<CVI_VP_VS_LONG_EARLY,
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[InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
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InstrStage<1, [CVI_XLSHF]>]>,
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InstrItinData<CVI_VP_DV , [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
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InstrStage<1, [CVI_XLSHF]>]>,
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InstrItinData<CVI_VS,
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[InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
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InstrStage<1, [CVI_SHIFT]>]>,
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InstrItinData<CVI_VINLANESAT,
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[InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
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InstrStage<1, [CVI_SHIFT]>]>,
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InstrItinData<CVI_VM_LD , [InstrStage<1, [SLOT0, SLOT1], 0>,
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InstrStage<1, [CVI_LD], 0>,
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InstrStage<1, [CVI_XLANE, CVI_SHIFT,
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CVI_MPY0, CVI_MPY1]>]>,
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InstrItinData<CVI_VM_TMP_LD,[InstrStage<1,[SLOT0, SLOT1], 0>,
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InstrStage<1, [CVI_LD]>]>,
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InstrItinData<CVI_VM_CUR_LD,[InstrStage<1,[SLOT0, SLOT1], 0>,
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InstrStage<1, [CVI_LD], 0>,
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InstrStage<1, [CVI_XLANE, CVI_SHIFT,
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CVI_MPY0, CVI_MPY1]>]>,
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InstrItinData<CVI_VM_VP_LDU,[InstrStage<1,[SLOT0], 0>,
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InstrStage<1, [SLOT1], 0>,
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InstrStage<1, [CVI_LD], 0>,
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InstrStage<1, [CVI_XLANE]>]>,
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InstrItinData<CVI_VM_ST , [InstrStage<1, [SLOT0], 0>,
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InstrStage<1, [CVI_ST], 0>,
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InstrStage<1, [CVI_XLANE, CVI_SHIFT,
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CVI_MPY0, CVI_MPY1]>]>,
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InstrItinData<CVI_VM_NEW_ST,[InstrStage<1,[SLOT0], 0>,
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InstrStage<1, [CVI_ST]>]>,
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InstrItinData<CVI_VM_STU , [InstrStage<1, [SLOT0], 0>,
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InstrStage<1, [SLOT1], 0>,
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InstrStage<1, [CVI_ST], 0>,
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InstrStage<1, [CVI_XLANE]>]>,
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InstrItinData<CVI_HIST , [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
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InstrStage<1, [CVI_ALL]>]>
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]>;
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def HexagonModelV60 : SchedMachineModel {
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// Max issue per cycle == bundle width.
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let IssueWidth = 4;
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let Itineraries = HexagonItinerariesV60;
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let LoadLatency = 1;
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let CompleteModel = 0;
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}
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//===----------------------------------------------------------------------===//
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// Hexagon V60 Resource Definitions -
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//===----------------------------------------------------------------------===//
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