Craig Topper 38e5713f51 [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. ... Summary: This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between Jcc instructions and condition codes. Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser. Reviewers: spatel, lebedev.ri, courbet, gchatelet, RKSimon Reviewed By: RKSimon Subscribers: MatzeB, qcolombet, eraman, hiraditya, arphaman, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60228 llvm-svn: 357802		2019-04-05 19:28:09 +00:00
..
test_copy_mismatch_types.mir
test_copy.mir
test_g_add.mir
test_g_addrspacecast.mir
test_g_bitcast.mir
test_g_build_vector_trunc.mir
test_g_build_vector.mir
test_g_concat_vectors.mir
test_g_constant.mir
test_g_extract.mir
test_g_fcmp.mir
test_g_fconstant.mir
test_g_gep.mir
test_g_icmp.mir
test_g_insert.mir	GlobalISel: Verify g_insert	2019-02-19 16:10:16 +00:00
test_g_inttoptr.mir
test_g_load.mir
test_g_phi.mir
test_g_ptrtoint.mir
test_g_select.mir
test_g_sextload.mir
test_g_store.mir
test_g_trunc.mir
test_g_zextload.mir
test_phis_precede_nonphis.mir
verifier-generic-extend-truncate.mir
verifier-generic-types-1.mir
verifier-generic-types-2.mir
verifier-implicit-virtreg-invalid-physreg-liveness.mir	[AMDGPU] Add support for immediate operand for S_ENDPGM	2019-03-12 09:52:58 +00:00
verifier-phi-fail0.mir	[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.	2019-04-05 19:28:09 +00:00
verifier-phi.mir	[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.	2019-04-05 19:28:09 +00:00
verifier-pseudo-terminators.mir
verify-regbankselected.mir
verify-selected.mir