mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-23 04:52:54 +02:00
afe2eccae3
Retrying after fixing after removing load-store factoring through
token factors in favor of improved token factor operand pruning
Simplify Consecutive Merge Store Candidate Search
Now that address aliasing is much less conservative, push through
simplified store merging search which only checks for parallel stores
through the chain subgraph. This is cleaner as the separation of
non-interfering loads/stores from the store-merging logic.
Whem merging stores, search up the chain through a single load, and
finds all possible stores by looking down from through a load and a
TokenFactor to all stores visited. This improves the quality of the
output SelectionDAG and generally the output CodeGen (with some
exceptions).
Additional Minor Changes:
1. Finishes removing unused AliasLoad code
2. Unifies the the chain aggregation in the merged stores across
code paths
3. Re-add the Store node to the worklist after calling
SimplifyDemandedBits.
4. Increase GatherAllAliasesMaxDepth from 6 to 18. That number is
arbitrary, but seemed sufficient to not cause regressions in
tests.
This finishes the change Matt Arsenault started in r246307 and
jyknight's original patch.
Many tests required some changes as memory operations are now
reorderable. Some tests relying on the order were changed to use
volatile memory operations
Noteworthy tests:
CodeGen/AArch64/argument-blocks.ll -
It's not entirely clear what the test_varargs_stackalign test is
supposed to be asserting, but the new code looks right.
CodeGen/AArch64/arm64-memset-inline.lli -
CodeGen/AArch64/arm64-stur.ll -
CodeGen/ARM/memset-inline.ll -
The backend now generates *worse* code due to store merging
succeeding, as we do do a 16-byte constant-zero store efficiently.
CodeGen/AArch64/merge-store.ll -
Improved, but there still seems to be an extraneous vector insert
from an element to itself?
CodeGen/PowerPC/ppc64-align-long-double.ll -
Worse code emitted in this case, due to the improved store->load
forwarding.
CodeGen/X86/dag-merge-fast-accesses.ll -
CodeGen/X86/MergeConsecutiveStores.ll -
CodeGen/X86/stores-merging.ll -
CodeGen/Mips/load-store-left-right.ll -
Restored correct merging of non-aligned stores
CodeGen/AMDGPU/promote-alloca-stored-pointer-value.ll -
Improved. Correctly merges buffer_store_dword calls
CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll -
Improved. Sidesteps loading a stored value and
merges two stores
CodeGen/X86/pr18023.ll -
This test has been removed, as it was asserting incorrect
behavior. Non-volatile stores *CAN* be moved past volatile loads,
and now are.
CodeGen/X86/vector-idiv.ll -
CodeGen/X86/vector-lzcnt-128.ll -
It's basically impossible to tell what these tests are actually
testing. But, looks like the code got better due to the memory
operations being recognized as non-aliasing.
CodeGen/X86/win32-eh.ll -
Both loads of the securitycookie are now merged.
Reviewers: arsenm, hfinkel, tstellarAMD, jyknight, nhaehnle
Subscribers: wdng, nhaehnle, nemanjai, arsenm, weimingz, niravd, RKSimon, aemerson, qcolombet, dsanders, resistor, tstellarAMD, t.p.northover, spatel
Differential Revision: https://reviews.llvm.org/D14834
llvm-svn: 289659
223 lines
10 KiB
LLVM
223 lines
10 KiB
LLVM
; RUN: llc -march=mips -relocation-model=static -mattr=+soft-float < %s | FileCheck --check-prefixes=ALL,SYM32,O32,O32BE %s
|
|
; RUN: llc -march=mipsel -relocation-model=static -mattr=+soft-float < %s | FileCheck --check-prefixes=ALL,SYM32,O32,O32LE %s
|
|
|
|
; RUN-TODO: llc -march=mips64 -relocation-model=static -mattr=+soft-float -target-abi o32 < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s
|
|
; RUN-TODO: llc -march=mips64el -relocation-model=static -mattr=+soft-float -target-abi o32 < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s
|
|
|
|
; RUN: llc -march=mips64 -relocation-model=static -mattr=+soft-float -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,NEW %s
|
|
; RUN: llc -march=mips64el -relocation-model=static -mattr=+soft-float -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,NEW %s
|
|
|
|
; RUN: llc -march=mips64 -relocation-model=static -mattr=+soft-float -target-abi n64 < %s | FileCheck --check-prefixes=ALL,SYM64,NEW %s
|
|
; RUN: llc -march=mips64el -relocation-model=static -mattr=+soft-float -target-abi n64 < %s | FileCheck --check-prefixes=ALL,SYM64,NEW %s
|
|
|
|
; Test the floating point arguments for all ABI's and byte orders as specified
|
|
; by section 5 of MD00305 (MIPS ABIs Described).
|
|
;
|
|
; N32/N64 are identical in this area so their checks have been combined into
|
|
; the 'NEW' prefix (the N stands for New).
|
|
|
|
@bytes = global [11 x i8] zeroinitializer
|
|
@dwords = global [11 x i64] zeroinitializer
|
|
@floats = global [11 x float] zeroinitializer
|
|
@doubles = global [11 x double] zeroinitializer
|
|
|
|
define void @double_args(double %a, double %b, double %c, double %d, double %e,
|
|
double %f, double %g, double %h, double %i) nounwind {
|
|
entry:
|
|
%0 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 1
|
|
store volatile double %a, double* %0
|
|
%1 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 2
|
|
store volatile double %b, double* %1
|
|
%2 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 3
|
|
store volatile double %c, double* %2
|
|
%3 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 4
|
|
store volatile double %d, double* %3
|
|
%4 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 5
|
|
store volatile double %e, double* %4
|
|
%5 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 6
|
|
store volatile double %f, double* %5
|
|
%6 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 7
|
|
store volatile double %g, double* %6
|
|
%7 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 8
|
|
store volatile double %h, double* %7
|
|
%8 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 9
|
|
store volatile double %i, double* %8
|
|
ret void
|
|
}
|
|
|
|
; ALL-LABEL: double_args:
|
|
; We won't test the way the global address is calculated in this test. This is
|
|
; just to get the register number for the other checks.
|
|
; SYM32-DAG: addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(doubles)
|
|
; SYM64-DAG: ld [[R2:\$[0-9]]], %got_disp(doubles)(
|
|
|
|
; The first four arguments are the same in O32/N32/N64.
|
|
; The first argument is floating point but soft-float is enabled so floating
|
|
; point registers are not used.
|
|
; O32-DAG: sw $4, 8([[R2]])
|
|
; O32-DAG: sw $5, 12([[R2]])
|
|
; NEW-DAG: sd $4, 8([[R2]])
|
|
|
|
; O32-DAG: sw $6, 16([[R2]])
|
|
; O32-DAG: sw $7, 20([[R2]])
|
|
; NEW-DAG: sd $5, 16([[R2]])
|
|
|
|
; O32 has run out of argument registers and starts using the stack
|
|
; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 16($sp)
|
|
; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 20($sp)
|
|
; O32-DAG: sw [[R3]], 24([[R2]])
|
|
; O32-DAG: sw [[R4]], 28([[R2]])
|
|
; NEW-DAG: sd $6, 24([[R2]])
|
|
|
|
; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 24($sp)
|
|
; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 28($sp)
|
|
; O32-DAG: sw [[R3]], 32([[R2]])
|
|
; O32-DAG: sw [[R4]], 36([[R2]])
|
|
; NEW-DAG: sd $7, 32([[R2]])
|
|
|
|
; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 32($sp)
|
|
; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 36($sp)
|
|
; O32-DAG: sw [[R3]], 40([[R2]])
|
|
; O32-DAG: sw [[R4]], 44([[R2]])
|
|
; NEW-DAG: sd $8, 40([[R2]])
|
|
|
|
; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 40($sp)
|
|
; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 44($sp)
|
|
; O32-DAG: sw [[R3]], 48([[R2]])
|
|
; O32-DAG: sw [[R4]], 52([[R2]])
|
|
; NEW-DAG: sd $9, 48([[R2]])
|
|
|
|
; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 48($sp)
|
|
; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 52($sp)
|
|
; O32-DAG: sw [[R3]], 56([[R2]])
|
|
; O32-DAG: sw [[R4]], 60([[R2]])
|
|
; NEW-DAG: sd $10, 56([[R2]])
|
|
|
|
; N32/N64 have run out of registers and starts using the stack too
|
|
; O32-DAG: lw [[R3:\$[0-9]+]], 56($sp)
|
|
; O32-DAG: lw [[R4:\$[0-9]+]], 60($sp)
|
|
; O32-DAG: sw [[R3]], 64([[R2]])
|
|
; O32-DAG: sw [[R4]], 68([[R2]])
|
|
; NEW-DAG: ld [[R3:\$[0-9]+]], 0($sp)
|
|
; NEW-DAG: sd $11, 64([[R2]])
|
|
|
|
define void @float_args(float %a, float %b, float %c, float %d, float %e,
|
|
float %f, float %g, float %h, float %i, float %j)
|
|
nounwind {
|
|
entry:
|
|
%0 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 1
|
|
store volatile float %a, float* %0
|
|
%1 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 2
|
|
store volatile float %b, float* %1
|
|
%2 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 3
|
|
store volatile float %c, float* %2
|
|
%3 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 4
|
|
store volatile float %d, float* %3
|
|
%4 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 5
|
|
store volatile float %e, float* %4
|
|
%5 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 6
|
|
store volatile float %f, float* %5
|
|
%6 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 7
|
|
store volatile float %g, float* %6
|
|
%7 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 8
|
|
store volatile float %h, float* %7
|
|
%8 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 9
|
|
store volatile float %i, float* %8
|
|
%9 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 10
|
|
store volatile float %j, float* %9
|
|
ret void
|
|
}
|
|
|
|
; ALL-LABEL: float_args:
|
|
; We won't test the way the global address is calculated in this test. This is
|
|
; just to get the register number for the other checks.
|
|
; SYM32-DAG: addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(floats)
|
|
; SYM64-DAG: ld [[R2:\$[0-9]]], %got_disp(floats)(
|
|
|
|
; The first four arguments are the same in O32/N32/N64.
|
|
; The first argument is floating point but soft-float is enabled so floating
|
|
; point registers are not used.
|
|
; MD00305 and GCC disagree on this one. MD00305 says that floats are treated
|
|
; as 8-byte aligned and occupy two slots on O32. GCC is treating them as 4-byte
|
|
; aligned and occupying one slot. We'll use GCC's definition.
|
|
; ALL-DAG: sw $4, 4([[R2]])
|
|
; ALL-DAG: sw $5, 8([[R2]])
|
|
; ALL-DAG: sw $6, 12([[R2]])
|
|
; ALL-DAG: sw $7, 16([[R2]])
|
|
|
|
; O32 has run out of argument registers and starts using the stack
|
|
; O32-DAG: lw [[R3:\$[0-9]+]], 16($sp)
|
|
; O32-DAG: sw [[R3]], 20([[R2]])
|
|
; NEW-DAG: sw $8, 20([[R2]])
|
|
|
|
; O32-DAG: lw [[R3:\$[0-9]+]], 20($sp)
|
|
; O32-DAG: sw [[R3]], 24([[R2]])
|
|
; NEW-DAG: sw $9, 24([[R2]])
|
|
|
|
; O32-DAG: lw [[R3:\$[0-9]+]], 24($sp)
|
|
; O32-DAG: sw [[R3]], 28([[R2]])
|
|
; NEW-DAG: sw $10, 28([[R2]])
|
|
|
|
; O32-DAG: lw [[R3:\$[0-9]+]], 28($sp)
|
|
; O32-DAG: sw [[R3]], 32([[R2]])
|
|
; NEW-DAG: sw $11, 32([[R2]])
|
|
|
|
; N32/N64 have run out of registers and start using the stack too
|
|
; O32-DAG: lw [[R3:\$[0-9]+]], 32($sp)
|
|
; O32-DAG: sw [[R3]], 36([[R2]])
|
|
; NEW-DAG: lw [[R3:\$[0-9]+]], 0($sp)
|
|
; NEW-DAG: sw [[R3]], 36([[R2]])
|
|
|
|
define void @double_arg2(i8 %a, double %b) nounwind {
|
|
entry:
|
|
%0 = getelementptr [11 x i8], [11 x i8]* @bytes, i32 0, i32 1
|
|
store volatile i8 %a, i8* %0
|
|
%1 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 1
|
|
store volatile double %b, double* %1
|
|
ret void
|
|
}
|
|
|
|
; ALL-LABEL: double_arg2:
|
|
; We won't test the way the global address is calculated in this test. This is
|
|
; just to get the register number for the other checks.
|
|
; SYM32-DAG: addiu [[R1:\$[0-9]+]], ${{[0-9]+}}, %lo(bytes)
|
|
; SYM64-DAG: ld [[R1:\$[0-9]]], %got_disp(bytes)(
|
|
; SYM32-DAG: addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(doubles)
|
|
; SYM64-DAG: ld [[R2:\$[0-9]]], %got_disp(doubles)(
|
|
|
|
; The first four arguments are the same in O32/N32/N64.
|
|
; The first argument isn't floating point so floating point registers are not
|
|
; used.
|
|
; The second slot is insufficiently aligned for double on O32 so it is skipped.
|
|
; Also, double occupies two slots on O32 and only one for N32/N64.
|
|
; ALL-DAG: sb $4, 1([[R1]])
|
|
; O32-DAG: sw $6, 8([[R2]])
|
|
; O32-DAG: sw $7, 12([[R2]])
|
|
; NEW-DAG: sd $5, 8([[R2]])
|
|
|
|
define void @float_arg2(i8 signext %a, float %b) nounwind {
|
|
entry:
|
|
%0 = getelementptr [11 x i8], [11 x i8]* @bytes, i32 0, i32 1
|
|
store volatile i8 %a, i8* %0
|
|
%1 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 1
|
|
store volatile float %b, float* %1
|
|
ret void
|
|
}
|
|
|
|
; ALL-LABEL: float_arg2:
|
|
; We won't test the way the global address is calculated in this test. This is
|
|
; just to get the register number for the other checks.
|
|
; SYM32-DAG: addiu [[R1:\$[0-9]+]], ${{[0-9]+}}, %lo(bytes)
|
|
; SYM64-DAG: ld [[R1:\$[0-9]]], %got_disp(bytes)(
|
|
; SYM32-DAG: addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(floats)
|
|
; SYM64-DAG: ld [[R2:\$[0-9]]], %got_disp(floats)(
|
|
|
|
; The first four arguments are the same in O32/N32/N64.
|
|
; The first argument isn't floating point so floating point registers are not
|
|
; used.
|
|
; MD00305 and GCC disagree on this one. MD00305 says that floats are treated
|
|
; as 8-byte aligned and occupy two slots on O32. GCC is treating them as 4-byte
|
|
; aligned and occupying one slot. We'll use GCC's definition.
|
|
; ALL-DAG: sb $4, 1([[R1]])
|
|
; ALL-DAG: sw $5, 4([[R2]])
|