1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-01 00:12:50 +01:00
llvm-mirror/test/CodeGen/X86/zero-remat.ll
Jakob Stoklund Olesen 5d6a4584d9 Make X86::FsFLD0SS / FsFLD0SD real pseudo-instructions.
Like V_SET0, these instructions are expanded by ExpandPostRA to xorps /
vxorps so they can participate in execution domain swizzling.

This also makes the AVX variants redundant.

llvm-svn: 145440
2011-11-29 22:27:25 +00:00

41 lines
752 B
LLVM

; RUN: llc < %s -march=x86-64 | FileCheck %s --check-prefix=CHECK-64
; RUN: llc < %s -march=x86-64 -o /dev/null -stats -info-output-file - | grep asm-printer | grep 12
; RUN: llc < %s -march=x86 | FileCheck %s --check-prefix=CHECK-32
declare void @bar(double %x)
declare void @barf(float %x)
define double @foo() nounwind {
call void @bar(double 0.0)
ret double 0.0
;CHECK-32: foo:
;CHECK-32: call
;CHECK-32: fldz
;CHECK-32: ret
;CHECK-64: foo:
;CHECK-64: xorps
;CHECK-64: call
;CHECK-64: xorps
;CHECK-64: ret
}
define float @foof() nounwind {
call void @barf(float 0.0)
ret float 0.0
;CHECK-32: foof:
;CHECK-32: call
;CHECK-32: fldz
;CHECK-32: ret
;CHECK-64: foof:
;CHECK-64: xorps
;CHECK-64: call
;CHECK-64: xorps
;CHECK-64: ret
}