Adhemerval Zanella 65794251d1 [AArch64] Add custom lowering for v4i8 trunc store ... This patch adds a custom trunc store lowering for v4i8 vector types. Since there is not v.4b register, the v4i8 is promoted to v4i16 (v.4h) and default action for v4i8 is to extract each element and issue 4 byte stores. A better strategy would be to extended the promoted v4i16 to v8i16 (with undef elements) and extract and store the word lane which represents the v4i8 subvectores. The construction: define void @foo(<4 x i16> %x, i8* nocapture %p) { %0 = trunc <4 x i16> %x to <4 x i8> %1 = bitcast i8* %p to <4 x i8>* store <4 x i8> %0, <4 x i8>* %1, align 4, !tbaa !2 ret void } Can be optimized from: umov w8, v0.h[3] umov w9, v0.h[2] umov w10, v0.h[1] umov w11, v0.h[0] strb w8, [x0, #3] strb w9, [x0, #2] strb w10, [x0, #1] strb w11, [x0] ret To: xtn v0.8b, v0.8h str s0, [x0] ret The patch also adjust the memory cost for autovectorization, so the C code: void foo (const int *src, int width, unsigned char *dst) { for (int i = 0; i < width; i++) *dst++ = *src++; } can be vectorized to: .LBB0_4: // %vector.body // =>This Inner Loop Header: Depth=1 ldr q0, [x0], #16 subs x12, x12, #4 // =4 xtn v0.4h, v0.4s xtn v0.8b, v0.8h st1 { v0.s }[0], [x2], #4 b.ne .LBB0_4 Instead of byte operations. llvm-svn: 335735		2018-06-27 13:58:46 +00:00
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AArch64	[AArch64] Add custom lowering for v4i8 trunc store	2018-06-27 13:58:46 +00:00
AMDGPU	[AMDGPU] Switch to the new addr space mapping by default	2018-02-02 16:07:16 +00:00
ARM	Convert an APInt to int64_t properly in TTI::getGEPCost().	2017-10-04 20:47:33 +00:00
PowerPC
SystemZ
X86	[X86][AVX] Reduce v4f64/v4i64 shuffle costs (PR37882)	2018-06-21 11:37:13 +00:00
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