Craig Topper b005c33640 [X86] Don't use aligned load/store instructions for fp128 if the load/store isn't aligned. ... Similarily, don't fold fp128 loads into SSE instructions if the load isn't aligned. Unless we're targeting an AMD CPU that doesn't check alignment on arithmetic instructions. Should fix PR38001 llvm-svn: 336121		2018-07-02 17:01:54 +00:00
..
AArch64	[AArch64][GlobalISel] Any-extend vararg parameters to stack slot size on Darwin.	2018-07-02 16:39:09 +00:00
AMDGPU	AMDGPU/GlobalISel: Make IMPLICIT_DEF of all sizes < 512 legal.	2018-06-30 04:09:44 +00:00
ARC
ARM	[ARM] Parallel DSP Pass	2018-06-28 12:55:29 +00:00
AVR
BPF
Generic	Implement strip.invariant.group	2018-07-02 04:49:30 +00:00
Hexagon	[DAGCombiner] Ensure we use the correct CC result type in visitSDIV (REAPPLIED)	2018-06-28 17:33:41 +00:00
Inputs
Lanai
Mips	[Mips][FastISel] Do not duplicate condition while lowering branches	2018-07-02 08:56:57 +00:00
MIR
MSP430
Nios2
NVPTX
PowerPC	[PowerPC] Don't make it as pre-inc candidate if displacement isn't 4's multiple for i64 pre-inc load/store	2018-07-02 05:46:09 +00:00
RISCV	[RISCV] Add machine function pass to merge base + offset	2018-06-27 20:51:42 +00:00
SPARC
SystemZ	Recommit r335333 "[MC] - Add .stack_size sections into groups and link them with .text"	2018-06-22 10:53:47 +00:00
Thumb
Thumb2
WebAssembly	[WebAssembly] Convert remaining tests from elf to wasm output format	2018-07-02 16:03:49 +00:00
WinCFGuard
WinEH
X86	[X86] Don't use aligned load/store instructions for fp128 if the load/store isn't aligned.	2018-07-02 17:01:54 +00:00
XCore