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87d13166c7
This is how it should've been and brings it more in line with std::string_view. There should be no functional change here. This is mostly mechanical from a custom clang-tidy check, with a lot of manual fixups. It uncovers a lot of minor inefficiencies. This doesn't actually modify StringRef yet, I'll do that in a follow-up.
885 lines
38 KiB
C++
885 lines
38 KiB
C++
//===- RISCVCompressInstEmitter.cpp - Generator for RISCV Compression -===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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// RISCVCompressInstEmitter implements a tablegen-driven CompressPat based
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// RISCV Instruction Compression mechanism.
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//
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//===--------------------------------------------------------------===//
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//
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// RISCVCompressInstEmitter implements a tablegen-driven CompressPat Instruction
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// Compression mechanism for generating RISCV compressed instructions
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// (C ISA Extension) from the expanded instruction form.
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// This tablegen backend processes CompressPat declarations in a
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// td file and generates all the required checks to validate the pattern
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// declarations; validate the input and output operands to generate the correct
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// compressed instructions. The checks include validating different types of
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// operands; register operands, immediate operands, fixed register and fixed
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// immediate inputs.
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//
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// Example:
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// class CompressPat<dag input, dag output> {
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// dag Input = input;
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// dag Output = output;
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// list<Predicate> Predicates = [];
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// }
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//
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// let Predicates = [HasStdExtC] in {
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// def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs1, GPRNoX0:$rs2),
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// (C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>;
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// }
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//
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// The result is an auto-generated header file
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// 'RISCVGenCompressInstEmitter.inc' which exports two functions for
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// compressing/uncompressing MCInst instructions, plus
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// some helper functions:
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//
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// bool compressInst(MCInst& OutInst, const MCInst &MI,
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// const MCSubtargetInfo &STI,
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// MCContext &Context);
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//
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// bool uncompressInst(MCInst& OutInst, const MCInst &MI,
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// const MCRegisterInfo &MRI,
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// const MCSubtargetInfo &STI);
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//
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// In addition, it exports a function for checking whether
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// an instruction is compressable:
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//
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// bool isCompressibleInst(const MachineInstr& MI,
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// const RISCVSubtarget *Subtarget,
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// const MCRegisterInfo &MRI,
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// const MCSubtargetInfo &STI);
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//
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// The clients that include this auto-generated header file and
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// invoke these functions can compress an instruction before emitting
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// it in the target-specific ASM or ELF streamer or can uncompress
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// an instruction before printing it when the expanded instruction
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// format aliases is favored.
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//===----------------------------------------------------------------------===//
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#include "CodeGenInstruction.h"
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#include "CodeGenTarget.h"
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#include "llvm/ADT/IndexedMap.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/ADT/StringMap.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/TableGen/Error.h"
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#include "llvm/TableGen/Record.h"
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#include "llvm/TableGen/TableGenBackend.h"
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#include <set>
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#include <vector>
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using namespace llvm;
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#define DEBUG_TYPE "compress-inst-emitter"
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namespace {
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class RISCVCompressInstEmitter {
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struct OpData {
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enum MapKind { Operand, Imm, Reg };
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MapKind Kind;
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union {
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unsigned Operand; // Operand number mapped to.
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uint64_t Imm; // Integer immediate value.
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Record *Reg; // Physical register.
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} Data;
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int TiedOpIdx = -1; // Tied operand index within the instruction.
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};
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struct CompressPat {
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CodeGenInstruction Source; // The source instruction definition.
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CodeGenInstruction Dest; // The destination instruction to transform to.
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std::vector<Record *>
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PatReqFeatures; // Required target features to enable pattern.
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IndexedMap<OpData>
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SourceOperandMap; // Maps operands in the Source Instruction to
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// the corresponding Dest instruction operand.
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IndexedMap<OpData>
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DestOperandMap; // Maps operands in the Dest Instruction
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// to the corresponding Source instruction operand.
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CompressPat(CodeGenInstruction &S, CodeGenInstruction &D,
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std::vector<Record *> RF, IndexedMap<OpData> &SourceMap,
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IndexedMap<OpData> &DestMap)
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: Source(S), Dest(D), PatReqFeatures(RF), SourceOperandMap(SourceMap),
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DestOperandMap(DestMap) {}
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};
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enum EmitterType { Compress, Uncompress, CheckCompress };
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RecordKeeper &Records;
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CodeGenTarget Target;
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SmallVector<CompressPat, 4> CompressPatterns;
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void addDagOperandMapping(Record *Rec, DagInit *Dag, CodeGenInstruction &Inst,
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IndexedMap<OpData> &OperandMap, bool IsSourceInst);
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void evaluateCompressPat(Record *Compress);
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void emitCompressInstEmitter(raw_ostream &o, EmitterType EType);
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bool validateTypes(Record *SubType, Record *Type, bool IsSourceInst);
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bool validateRegister(Record *Reg, Record *RegClass);
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void createDagOperandMapping(Record *Rec, StringMap<unsigned> &SourceOperands,
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StringMap<unsigned> &DestOperands,
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DagInit *SourceDag, DagInit *DestDag,
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IndexedMap<OpData> &SourceOperandMap);
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void createInstOperandMapping(Record *Rec, DagInit *SourceDag,
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DagInit *DestDag,
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IndexedMap<OpData> &SourceOperandMap,
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IndexedMap<OpData> &DestOperandMap,
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StringMap<unsigned> &SourceOperands,
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CodeGenInstruction &DestInst);
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public:
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RISCVCompressInstEmitter(RecordKeeper &R) : Records(R), Target(R) {}
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void run(raw_ostream &o);
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};
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} // End anonymous namespace.
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bool RISCVCompressInstEmitter::validateRegister(Record *Reg, Record *RegClass) {
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assert(Reg->isSubClassOf("Register") && "Reg record should be a Register\n");
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assert(RegClass->isSubClassOf("RegisterClass") && "RegClass record should be"
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" a RegisterClass\n");
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const CodeGenRegisterClass &RC = Target.getRegisterClass(RegClass);
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const CodeGenRegister *R = Target.getRegisterByName(Reg->getName().lower());
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assert((R != nullptr) &&
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("Register" + Reg->getName().str() + " not defined!!\n").c_str());
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return RC.contains(R);
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}
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bool RISCVCompressInstEmitter::validateTypes(Record *DagOpType,
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Record *InstOpType,
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bool IsSourceInst) {
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if (DagOpType == InstOpType)
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return true;
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// Only source instruction operands are allowed to not match Input Dag
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// operands.
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if (!IsSourceInst)
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return false;
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if (DagOpType->isSubClassOf("RegisterClass") &&
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InstOpType->isSubClassOf("RegisterClass")) {
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const CodeGenRegisterClass &RC = Target.getRegisterClass(InstOpType);
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const CodeGenRegisterClass &SubRC = Target.getRegisterClass(DagOpType);
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return RC.hasSubClass(&SubRC);
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}
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// At this point either or both types are not registers, reject the pattern.
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if (DagOpType->isSubClassOf("RegisterClass") ||
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InstOpType->isSubClassOf("RegisterClass"))
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return false;
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// Let further validation happen when compress()/uncompress() functions are
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// invoked.
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LLVM_DEBUG(dbgs() << (IsSourceInst ? "Input" : "Output")
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<< " Dag Operand Type: '" << DagOpType->getName()
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<< "' and "
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<< "Instruction Operand Type: '" << InstOpType->getName()
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<< "' can't be checked at pattern validation time!\n");
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return true;
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}
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/// The patterns in the Dag contain different types of operands:
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/// Register operands, e.g.: GPRC:$rs1; Fixed registers, e.g: X1; Immediate
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/// operands, e.g.: simm6:$imm; Fixed immediate operands, e.g.: 0. This function
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/// maps Dag operands to its corresponding instruction operands. For register
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/// operands and fixed registers it expects the Dag operand type to be contained
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/// in the instantiated instruction operand type. For immediate operands and
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/// immediates no validation checks are enforced at pattern validation time.
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void RISCVCompressInstEmitter::addDagOperandMapping(
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Record *Rec, DagInit *Dag, CodeGenInstruction &Inst,
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IndexedMap<OpData> &OperandMap, bool IsSourceInst) {
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// TiedCount keeps track of the number of operands skipped in Inst
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// operands list to get to the corresponding Dag operand. This is
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// necessary because the number of operands in Inst might be greater
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// than number of operands in the Dag due to how tied operands
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// are represented.
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unsigned TiedCount = 0;
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for (unsigned i = 0, e = Inst.Operands.size(); i != e; ++i) {
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int TiedOpIdx = Inst.Operands[i].getTiedRegister();
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if (-1 != TiedOpIdx) {
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// Set the entry in OperandMap for the tied operand we're skipping.
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OperandMap[i].Kind = OperandMap[TiedOpIdx].Kind;
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OperandMap[i].Data = OperandMap[TiedOpIdx].Data;
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TiedCount++;
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continue;
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}
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if (DefInit *DI = dyn_cast<DefInit>(Dag->getArg(i - TiedCount))) {
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if (DI->getDef()->isSubClassOf("Register")) {
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// Check if the fixed register belongs to the Register class.
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if (!validateRegister(DI->getDef(), Inst.Operands[i].Rec))
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PrintFatalError(Rec->getLoc(),
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"Error in Dag '" + Dag->getAsString() +
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"'Register: '" + DI->getDef()->getName() +
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"' is not in register class '" +
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Inst.Operands[i].Rec->getName() + "'");
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OperandMap[i].Kind = OpData::Reg;
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OperandMap[i].Data.Reg = DI->getDef();
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continue;
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}
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// Validate that Dag operand type matches the type defined in the
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// corresponding instruction. Operands in the input Dag pattern are
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// allowed to be a subclass of the type specified in corresponding
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// instruction operand instead of being an exact match.
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if (!validateTypes(DI->getDef(), Inst.Operands[i].Rec, IsSourceInst))
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PrintFatalError(Rec->getLoc(),
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"Error in Dag '" + Dag->getAsString() + "'. Operand '" +
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Dag->getArgNameStr(i - TiedCount) + "' has type '" +
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DI->getDef()->getName() +
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"' which does not match the type '" +
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Inst.Operands[i].Rec->getName() +
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"' in the corresponding instruction operand!");
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OperandMap[i].Kind = OpData::Operand;
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} else if (IntInit *II = dyn_cast<IntInit>(Dag->getArg(i - TiedCount))) {
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// Validate that corresponding instruction operand expects an immediate.
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if (Inst.Operands[i].Rec->isSubClassOf("RegisterClass"))
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PrintFatalError(
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Rec->getLoc(),
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("Error in Dag '" + Dag->getAsString() + "' Found immediate: '" +
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II->getAsString() +
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"' but corresponding instruction operand expected a register!"));
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// No pattern validation check possible for values of fixed immediate.
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OperandMap[i].Kind = OpData::Imm;
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OperandMap[i].Data.Imm = II->getValue();
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LLVM_DEBUG(
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dbgs() << " Found immediate '" << II->getValue() << "' at "
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<< (IsSourceInst ? "input " : "output ")
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<< "Dag. No validation time check possible for values of "
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"fixed immediate.\n");
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} else
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llvm_unreachable("Unhandled CompressPat argument type!");
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}
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}
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// Verify the Dag operand count is enough to build an instruction.
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static bool verifyDagOpCount(CodeGenInstruction &Inst, DagInit *Dag,
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bool IsSource) {
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if (Dag->getNumArgs() == Inst.Operands.size())
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return true;
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// Source instructions are non compressed instructions and don't have tied
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// operands.
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if (IsSource)
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PrintFatalError(Inst.TheDef->getLoc(),
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"Input operands for Inst '" + Inst.TheDef->getName() +
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"' and input Dag operand count mismatch");
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// The Dag can't have more arguments than the Instruction.
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if (Dag->getNumArgs() > Inst.Operands.size())
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PrintFatalError(Inst.TheDef->getLoc(),
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"Inst '" + Inst.TheDef->getName() +
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"' and Dag operand count mismatch");
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// The Instruction might have tied operands so the Dag might have
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// a fewer operand count.
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unsigned RealCount = Inst.Operands.size();
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for (unsigned i = 0; i < Inst.Operands.size(); i++)
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if (Inst.Operands[i].getTiedRegister() != -1)
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--RealCount;
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if (Dag->getNumArgs() != RealCount)
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PrintFatalError(Inst.TheDef->getLoc(),
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"Inst '" + Inst.TheDef->getName() +
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"' and Dag operand count mismatch");
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return true;
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}
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static bool validateArgsTypes(Init *Arg1, Init *Arg2) {
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DefInit *Type1 = dyn_cast<DefInit>(Arg1);
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DefInit *Type2 = dyn_cast<DefInit>(Arg2);
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assert(Type1 && ("Arg1 type not found\n"));
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assert(Type2 && ("Arg2 type not found\n"));
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return Type1->getDef() == Type2->getDef();
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}
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// Creates a mapping between the operand name in the Dag (e.g. $rs1) and
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// its index in the list of Dag operands and checks that operands with the same
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// name have the same types. For example in 'C_ADD $rs1, $rs2' we generate the
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// mapping $rs1 --> 0, $rs2 ---> 1. If the operand appears twice in the (tied)
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// same Dag we use the last occurrence for indexing.
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void RISCVCompressInstEmitter::createDagOperandMapping(
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Record *Rec, StringMap<unsigned> &SourceOperands,
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StringMap<unsigned> &DestOperands, DagInit *SourceDag, DagInit *DestDag,
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IndexedMap<OpData> &SourceOperandMap) {
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for (unsigned i = 0; i < DestDag->getNumArgs(); ++i) {
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// Skip fixed immediates and registers, they were handled in
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// addDagOperandMapping.
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if ("" == DestDag->getArgNameStr(i))
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continue;
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DestOperands[DestDag->getArgNameStr(i)] = i;
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}
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for (unsigned i = 0; i < SourceDag->getNumArgs(); ++i) {
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// Skip fixed immediates and registers, they were handled in
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// addDagOperandMapping.
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if ("" == SourceDag->getArgNameStr(i))
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continue;
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StringMap<unsigned>::iterator it =
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SourceOperands.find(SourceDag->getArgNameStr(i));
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if (it != SourceOperands.end()) {
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// Operand sharing the same name in the Dag should be mapped as tied.
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SourceOperandMap[i].TiedOpIdx = it->getValue();
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if (!validateArgsTypes(SourceDag->getArg(it->getValue()),
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SourceDag->getArg(i)))
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PrintFatalError(Rec->getLoc(),
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"Input Operand '" + SourceDag->getArgNameStr(i) +
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"' has a mismatched tied operand!\n");
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}
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it = DestOperands.find(SourceDag->getArgNameStr(i));
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if (it == DestOperands.end())
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PrintFatalError(Rec->getLoc(), "Operand " + SourceDag->getArgNameStr(i) +
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" defined in Input Dag but not used in"
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" Output Dag!\n");
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// Input Dag operand types must match output Dag operand type.
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if (!validateArgsTypes(DestDag->getArg(it->getValue()),
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SourceDag->getArg(i)))
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PrintFatalError(Rec->getLoc(), "Type mismatch between Input and "
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"Output Dag operand '" +
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SourceDag->getArgNameStr(i) + "'!");
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SourceOperands[SourceDag->getArgNameStr(i)] = i;
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}
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}
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/// Map operand names in the Dag to their index in both corresponding input and
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/// output instructions. Validate that operands defined in the input are
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/// used in the output pattern while populating the maps.
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void RISCVCompressInstEmitter::createInstOperandMapping(
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Record *Rec, DagInit *SourceDag, DagInit *DestDag,
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IndexedMap<OpData> &SourceOperandMap, IndexedMap<OpData> &DestOperandMap,
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StringMap<unsigned> &SourceOperands, CodeGenInstruction &DestInst) {
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// TiedCount keeps track of the number of operands skipped in Inst
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// operands list to get to the corresponding Dag operand.
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unsigned TiedCount = 0;
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LLVM_DEBUG(dbgs() << " Operand mapping:\n Source Dest\n");
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for (unsigned i = 0, e = DestInst.Operands.size(); i != e; ++i) {
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int TiedInstOpIdx = DestInst.Operands[i].getTiedRegister();
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if (TiedInstOpIdx != -1) {
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++TiedCount;
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DestOperandMap[i].Data = DestOperandMap[TiedInstOpIdx].Data;
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DestOperandMap[i].Kind = DestOperandMap[TiedInstOpIdx].Kind;
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if (DestOperandMap[i].Kind == OpData::Operand)
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// No need to fill the SourceOperandMap here since it was mapped to
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// destination operand 'TiedInstOpIdx' in a previous iteration.
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LLVM_DEBUG(dbgs() << " " << DestOperandMap[i].Data.Operand
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<< " ====> " << i
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<< " Dest operand tied with operand '"
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<< TiedInstOpIdx << "'\n");
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continue;
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}
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// Skip fixed immediates and registers, they were handled in
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// addDagOperandMapping.
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if (DestOperandMap[i].Kind != OpData::Operand)
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continue;
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unsigned DagArgIdx = i - TiedCount;
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StringMap<unsigned>::iterator SourceOp =
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SourceOperands.find(DestDag->getArgNameStr(DagArgIdx));
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if (SourceOp == SourceOperands.end())
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PrintFatalError(Rec->getLoc(),
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"Output Dag operand '" +
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DestDag->getArgNameStr(DagArgIdx) +
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"' has no matching input Dag operand.");
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assert(DestDag->getArgNameStr(DagArgIdx) ==
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SourceDag->getArgNameStr(SourceOp->getValue()) &&
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"Incorrect operand mapping detected!\n");
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DestOperandMap[i].Data.Operand = SourceOp->getValue();
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SourceOperandMap[SourceOp->getValue()].Data.Operand = i;
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LLVM_DEBUG(dbgs() << " " << SourceOp->getValue() << " ====> " << i
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<< "\n");
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}
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}
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/// Validates the CompressPattern and create operand mapping.
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/// These are the checks to validate a CompressPat pattern declarations.
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/// Error out with message under these conditions:
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/// - Dag Input opcode is an expanded instruction and Dag Output opcode is a
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/// compressed instruction.
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/// - Operands in Dag Input must be all used in Dag Output.
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/// Register Operand type in Dag Input Type must be contained in the
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/// corresponding Source Instruction type.
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/// - Register Operand type in Dag Input must be the same as in Dag Ouput.
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/// - Register Operand type in Dag Output must be the same as the
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/// corresponding Destination Inst type.
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/// - Immediate Operand type in Dag Input must be the same as in Dag Ouput.
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/// - Immediate Operand type in Dag Ouput must be the same as the corresponding
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/// Destination Instruction type.
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/// - Fixed register must be contained in the corresponding Source Instruction
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/// type.
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/// - Fixed register must be contained in the corresponding Destination
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/// Instruction type. Warning message printed under these conditions:
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/// - Fixed immediate in Dag Input or Dag Ouput cannot be checked at this time
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/// and generate warning.
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/// - Immediate operand type in Dag Input differs from the corresponding Source
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/// Instruction type and generate a warning.
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void RISCVCompressInstEmitter::evaluateCompressPat(Record *Rec) {
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// Validate input Dag operands.
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DagInit *SourceDag = Rec->getValueAsDag("Input");
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assert(SourceDag && "Missing 'Input' in compress pattern!");
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LLVM_DEBUG(dbgs() << "Input: " << *SourceDag << "\n");
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// Checking we are transforming from compressed to uncompressed instructions.
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Record *Operator = SourceDag->getOperatorAsDef(Rec->getLoc());
|
|
if (!Operator->isSubClassOf("RVInst"))
|
|
PrintFatalError(Rec->getLoc(), "Input instruction '" + Operator->getName() +
|
|
"' is not a 32 bit wide instruction!");
|
|
CodeGenInstruction SourceInst(Operator);
|
|
verifyDagOpCount(SourceInst, SourceDag, true);
|
|
|
|
// Validate output Dag operands.
|
|
DagInit *DestDag = Rec->getValueAsDag("Output");
|
|
assert(DestDag && "Missing 'Output' in compress pattern!");
|
|
LLVM_DEBUG(dbgs() << "Output: " << *DestDag << "\n");
|
|
|
|
Record *DestOperator = DestDag->getOperatorAsDef(Rec->getLoc());
|
|
if (!DestOperator->isSubClassOf("RVInst16"))
|
|
PrintFatalError(Rec->getLoc(), "Output instruction '" +
|
|
DestOperator->getName() +
|
|
"' is not a 16 bit wide instruction!");
|
|
CodeGenInstruction DestInst(DestOperator);
|
|
verifyDagOpCount(DestInst, DestDag, false);
|
|
|
|
// Fill the mapping from the source to destination instructions.
|
|
|
|
IndexedMap<OpData> SourceOperandMap;
|
|
SourceOperandMap.grow(SourceInst.Operands.size());
|
|
// Create a mapping between source Dag operands and source Inst operands.
|
|
addDagOperandMapping(Rec, SourceDag, SourceInst, SourceOperandMap,
|
|
/*IsSourceInst*/ true);
|
|
|
|
IndexedMap<OpData> DestOperandMap;
|
|
DestOperandMap.grow(DestInst.Operands.size());
|
|
// Create a mapping between destination Dag operands and destination Inst
|
|
// operands.
|
|
addDagOperandMapping(Rec, DestDag, DestInst, DestOperandMap,
|
|
/*IsSourceInst*/ false);
|
|
|
|
StringMap<unsigned> SourceOperands;
|
|
StringMap<unsigned> DestOperands;
|
|
createDagOperandMapping(Rec, SourceOperands, DestOperands, SourceDag, DestDag,
|
|
SourceOperandMap);
|
|
// Create operand mapping between the source and destination instructions.
|
|
createInstOperandMapping(Rec, SourceDag, DestDag, SourceOperandMap,
|
|
DestOperandMap, SourceOperands, DestInst);
|
|
|
|
// Get the target features for the CompressPat.
|
|
std::vector<Record *> PatReqFeatures;
|
|
std::vector<Record *> RF = Rec->getValueAsListOfDefs("Predicates");
|
|
copy_if(RF, std::back_inserter(PatReqFeatures), [](Record *R) {
|
|
return R->getValueAsBit("AssemblerMatcherPredicate");
|
|
});
|
|
|
|
CompressPatterns.push_back(CompressPat(SourceInst, DestInst, PatReqFeatures,
|
|
SourceOperandMap, DestOperandMap));
|
|
}
|
|
|
|
static void getReqFeatures(std::set<StringRef> &FeaturesSet,
|
|
const std::vector<Record *> &ReqFeatures) {
|
|
for (auto &R : ReqFeatures) {
|
|
StringRef AsmCondString = R->getValueAsString("AssemblerCondString");
|
|
|
|
// AsmCondString has syntax [!]F(,[!]F)*
|
|
SmallVector<StringRef, 4> Ops;
|
|
SplitString(AsmCondString, Ops, ",");
|
|
assert(!Ops.empty() && "AssemblerCondString cannot be empty");
|
|
for (auto &Op : Ops) {
|
|
assert(!Op.empty() && "Empty operator");
|
|
FeaturesSet.insert(Op);
|
|
}
|
|
}
|
|
}
|
|
|
|
static unsigned getPredicates(DenseMap<const Record *, unsigned> &PredicateMap,
|
|
std::vector<const Record *> &Predicates,
|
|
Record *Rec, StringRef Name) {
|
|
unsigned Entry = PredicateMap[Rec];
|
|
if (Entry)
|
|
return Entry;
|
|
|
|
if (!Rec->isValueUnset(Name)) {
|
|
Predicates.push_back(Rec);
|
|
Entry = Predicates.size();
|
|
PredicateMap[Rec] = Entry;
|
|
return Entry;
|
|
}
|
|
|
|
PrintFatalError(Rec->getLoc(), "No " + Name +
|
|
" predicate on this operand at all: '" + Rec->getName().str() + "'");
|
|
return 0;
|
|
}
|
|
|
|
static void printPredicates(std::vector<const Record *> &Predicates,
|
|
StringRef Name, raw_ostream &o) {
|
|
for (unsigned i = 0; i < Predicates.size(); ++i) {
|
|
Init *Pred = Predicates[i]->getValueInit(Name);
|
|
if (CodeInit *SI = dyn_cast<CodeInit>(Pred))
|
|
o << " case " << i + 1 << ": {\n"
|
|
<< " // " << Predicates[i]->getName().str() << "\n"
|
|
<< " " << SI->getValue() << "\n"
|
|
<< " }\n";
|
|
else
|
|
llvm_unreachable("Unexpected predicate field!");
|
|
}
|
|
}
|
|
|
|
static std::string mergeCondAndCode(raw_string_ostream &CondStream,
|
|
raw_string_ostream &CodeStream) {
|
|
std::string S;
|
|
raw_string_ostream CombinedStream(S);
|
|
CombinedStream.indent(4)
|
|
<< "if ("
|
|
<< CondStream.str().substr(
|
|
6, CondStream.str().length() -
|
|
10) // remove first indentation and last '&&'.
|
|
<< ") {\n";
|
|
CombinedStream << CodeStream.str();
|
|
CombinedStream.indent(4) << " return true;\n";
|
|
CombinedStream.indent(4) << "} // if\n";
|
|
return CombinedStream.str();
|
|
}
|
|
|
|
void RISCVCompressInstEmitter::emitCompressInstEmitter(raw_ostream &o,
|
|
EmitterType EType) {
|
|
Record *AsmWriter = Target.getAsmWriter();
|
|
if (!AsmWriter->getValueAsInt("PassSubtarget"))
|
|
PrintFatalError(AsmWriter->getLoc(),
|
|
"'PassSubtarget' is false. SubTargetInfo object is needed "
|
|
"for target features.\n");
|
|
|
|
std::string Namespace = std::string(Target.getName());
|
|
|
|
// Sort entries in CompressPatterns to handle instructions that can have more
|
|
// than one candidate for compression\uncompression, e.g ADD can be
|
|
// transformed to a C_ADD or a C_MV. When emitting 'uncompress()' function the
|
|
// source and destination are flipped and the sort key needs to change
|
|
// accordingly.
|
|
llvm::stable_sort(CompressPatterns,
|
|
[EType](const CompressPat &LHS, const CompressPat &RHS) {
|
|
if (EType == EmitterType::Compress ||
|
|
EType == EmitterType::CheckCompress)
|
|
return (LHS.Source.TheDef->getName().str() <
|
|
RHS.Source.TheDef->getName().str());
|
|
else
|
|
return (LHS.Dest.TheDef->getName().str() <
|
|
RHS.Dest.TheDef->getName().str());
|
|
});
|
|
|
|
// A list of MCOperandPredicates for all operands in use, and the reverse map.
|
|
std::vector<const Record *> MCOpPredicates;
|
|
DenseMap<const Record *, unsigned> MCOpPredicateMap;
|
|
// A list of ImmLeaf Predicates for all operands in use, and the reverse map.
|
|
std::vector<const Record *> ImmLeafPredicates;
|
|
DenseMap<const Record *, unsigned> ImmLeafPredicateMap;
|
|
|
|
std::string F;
|
|
std::string FH;
|
|
raw_string_ostream Func(F);
|
|
raw_string_ostream FuncH(FH);
|
|
bool NeedMRI = false;
|
|
|
|
if (EType == EmitterType::Compress)
|
|
o << "\n#ifdef GEN_COMPRESS_INSTR\n"
|
|
<< "#undef GEN_COMPRESS_INSTR\n\n";
|
|
else if (EType == EmitterType::Uncompress)
|
|
o << "\n#ifdef GEN_UNCOMPRESS_INSTR\n"
|
|
<< "#undef GEN_UNCOMPRESS_INSTR\n\n";
|
|
else if (EType == EmitterType::CheckCompress)
|
|
o << "\n#ifdef GEN_CHECK_COMPRESS_INSTR\n"
|
|
<< "#undef GEN_CHECK_COMPRESS_INSTR\n\n";
|
|
|
|
if (EType == EmitterType::Compress) {
|
|
FuncH << "static bool compressInst(MCInst& OutInst,\n";
|
|
FuncH.indent(25) << "const MCInst &MI,\n";
|
|
FuncH.indent(25) << "const MCSubtargetInfo &STI,\n";
|
|
FuncH.indent(25) << "MCContext &Context) {\n";
|
|
} else if (EType == EmitterType::Uncompress){
|
|
FuncH << "static bool uncompressInst(MCInst& OutInst,\n";
|
|
FuncH.indent(27) << "const MCInst &MI,\n";
|
|
FuncH.indent(27) << "const MCRegisterInfo &MRI,\n";
|
|
FuncH.indent(27) << "const MCSubtargetInfo &STI) {\n";
|
|
} else if (EType == EmitterType::CheckCompress) {
|
|
FuncH << "static bool isCompressibleInst(const MachineInstr& MI,\n";
|
|
FuncH.indent(27) << "const RISCVSubtarget *Subtarget,\n";
|
|
FuncH.indent(27) << "const MCRegisterInfo &MRI,\n";
|
|
FuncH.indent(27) << "const MCSubtargetInfo &STI) {\n";
|
|
}
|
|
|
|
if (CompressPatterns.empty()) {
|
|
o << FuncH.str();
|
|
o.indent(2) << "return false;\n}\n";
|
|
if (EType == EmitterType::Compress)
|
|
o << "\n#endif //GEN_COMPRESS_INSTR\n";
|
|
else if (EType == EmitterType::Uncompress)
|
|
o << "\n#endif //GEN_UNCOMPRESS_INSTR\n\n";
|
|
else if (EType == EmitterType::CheckCompress)
|
|
o << "\n#endif //GEN_CHECK_COMPRESS_INSTR\n\n";
|
|
return;
|
|
}
|
|
|
|
std::string CaseString("");
|
|
raw_string_ostream CaseStream(CaseString);
|
|
std::string PrevOp("");
|
|
std::string CurOp("");
|
|
CaseStream << " switch (MI.getOpcode()) {\n";
|
|
CaseStream << " default: return false;\n";
|
|
|
|
bool CompressOrCheck =
|
|
EType == EmitterType::Compress || EType == EmitterType::CheckCompress;
|
|
bool CompressOrUncompress =
|
|
EType == EmitterType::Compress || EType == EmitterType::Uncompress;
|
|
|
|
for (auto &CompressPat : CompressPatterns) {
|
|
std::string CondString;
|
|
std::string CodeString;
|
|
raw_string_ostream CondStream(CondString);
|
|
raw_string_ostream CodeStream(CodeString);
|
|
CodeGenInstruction &Source =
|
|
CompressOrCheck ? CompressPat.Source : CompressPat.Dest;
|
|
CodeGenInstruction &Dest =
|
|
CompressOrCheck ? CompressPat.Dest : CompressPat.Source;
|
|
IndexedMap<OpData> SourceOperandMap = CompressOrCheck ?
|
|
CompressPat.SourceOperandMap : CompressPat.DestOperandMap;
|
|
IndexedMap<OpData> &DestOperandMap = CompressOrCheck ?
|
|
CompressPat.DestOperandMap : CompressPat.SourceOperandMap;
|
|
|
|
CurOp = Source.TheDef->getName().str();
|
|
// Check current and previous opcode to decide to continue or end a case.
|
|
if (CurOp != PrevOp) {
|
|
if (PrevOp != "")
|
|
CaseStream.indent(6) << "break;\n } // case " + PrevOp + "\n";
|
|
CaseStream.indent(4) << "case " + Namespace + "::" + CurOp + ": {\n";
|
|
}
|
|
|
|
std::set<StringRef> FeaturesSet;
|
|
// Add CompressPat required features.
|
|
getReqFeatures(FeaturesSet, CompressPat.PatReqFeatures);
|
|
|
|
// Add Dest instruction required features.
|
|
std::vector<Record *> ReqFeatures;
|
|
std::vector<Record *> RF = Dest.TheDef->getValueAsListOfDefs("Predicates");
|
|
copy_if(RF, std::back_inserter(ReqFeatures), [](Record *R) {
|
|
return R->getValueAsBit("AssemblerMatcherPredicate");
|
|
});
|
|
getReqFeatures(FeaturesSet, ReqFeatures);
|
|
|
|
// Emit checks for all required features.
|
|
for (auto &Op : FeaturesSet) {
|
|
if (Op[0] == '!')
|
|
CondStream.indent(6) << ("!STI.getFeatureBits()[" + Namespace +
|
|
"::" + Op.substr(1) + "]")
|
|
.str() +
|
|
" &&\n";
|
|
else
|
|
CondStream.indent(6)
|
|
<< ("STI.getFeatureBits()[" + Namespace + "::" + Op + "]").str() +
|
|
" &&\n";
|
|
}
|
|
|
|
// Start Source Inst operands validation.
|
|
unsigned OpNo = 0;
|
|
for (OpNo = 0; OpNo < Source.Operands.size(); ++OpNo) {
|
|
if (SourceOperandMap[OpNo].TiedOpIdx != -1) {
|
|
if (Source.Operands[OpNo].Rec->isSubClassOf("RegisterClass"))
|
|
CondStream.indent(6)
|
|
<< "(MI.getOperand("
|
|
<< std::to_string(OpNo) + ").getReg() == MI.getOperand("
|
|
<< std::to_string(SourceOperandMap[OpNo].TiedOpIdx)
|
|
<< ").getReg()) &&\n";
|
|
else
|
|
PrintFatalError("Unexpected tied operand types!\n");
|
|
}
|
|
// Check for fixed immediates\registers in the source instruction.
|
|
switch (SourceOperandMap[OpNo].Kind) {
|
|
case OpData::Operand:
|
|
// We don't need to do anything for source instruction operand checks.
|
|
break;
|
|
case OpData::Imm:
|
|
CondStream.indent(6)
|
|
<< "(MI.getOperand(" + std::to_string(OpNo) + ").isImm()) &&\n" +
|
|
" (MI.getOperand(" + std::to_string(OpNo) +
|
|
").getImm() == " +
|
|
std::to_string(SourceOperandMap[OpNo].Data.Imm) + ") &&\n";
|
|
break;
|
|
case OpData::Reg: {
|
|
Record *Reg = SourceOperandMap[OpNo].Data.Reg;
|
|
CondStream.indent(6) << "(MI.getOperand(" + std::to_string(OpNo) +
|
|
").getReg() == " + Namespace +
|
|
"::" + Reg->getName().str() + ") &&\n";
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
CodeStream.indent(6) << "// " + Dest.AsmString + "\n";
|
|
if (CompressOrUncompress)
|
|
CodeStream.indent(6) << "OutInst.setOpcode(" + Namespace +
|
|
"::" + Dest.TheDef->getName().str() + ");\n";
|
|
OpNo = 0;
|
|
for (const auto &DestOperand : Dest.Operands) {
|
|
CodeStream.indent(6) << "// Operand: " + DestOperand.Name + "\n";
|
|
switch (DestOperandMap[OpNo].Kind) {
|
|
case OpData::Operand: {
|
|
unsigned OpIdx = DestOperandMap[OpNo].Data.Operand;
|
|
// Check that the operand in the Source instruction fits
|
|
// the type for the Dest instruction.
|
|
if (DestOperand.Rec->isSubClassOf("RegisterClass")) {
|
|
NeedMRI = true;
|
|
// This is a register operand. Check the register class.
|
|
// Don't check register class if this is a tied operand, it was done
|
|
// for the operand its tied to.
|
|
if (DestOperand.getTiedRegister() == -1)
|
|
CondStream.indent(6)
|
|
<< "(MRI.getRegClass(" + Namespace +
|
|
"::" + DestOperand.Rec->getName().str() +
|
|
"RegClassID).contains(" + "MI.getOperand(" +
|
|
std::to_string(OpIdx) + ").getReg())) &&\n";
|
|
|
|
if (CompressOrUncompress)
|
|
CodeStream.indent(6) << "OutInst.addOperand(MI.getOperand(" +
|
|
std::to_string(OpIdx) + "));\n";
|
|
} else {
|
|
// Handling immediate operands.
|
|
if (CompressOrUncompress) {
|
|
unsigned Entry = getPredicates(MCOpPredicateMap, MCOpPredicates,
|
|
DestOperand.Rec, StringRef("MCOperandPredicate"));
|
|
CondStream.indent(6) << Namespace + "ValidateMCOperand(" +
|
|
"MI.getOperand(" + std::to_string(OpIdx) +
|
|
"), STI, " + std::to_string(Entry) +
|
|
") &&\n";
|
|
} else {
|
|
unsigned Entry = getPredicates(ImmLeafPredicateMap, ImmLeafPredicates,
|
|
DestOperand.Rec, StringRef("ImmediateCode"));
|
|
CondStream.indent(6) << "MI.getOperand(" + std::to_string(OpIdx) +
|
|
").isImm() && \n";
|
|
CondStream.indent(6) << Namespace + "ValidateMachineOperand(" +
|
|
"MI.getOperand(" + std::to_string(OpIdx) +
|
|
"), Subtarget, " + std::to_string(Entry) +
|
|
") &&\n";
|
|
}
|
|
if (CompressOrUncompress)
|
|
CodeStream.indent(6) << "OutInst.addOperand(MI.getOperand(" +
|
|
std::to_string(OpIdx) + "));\n";
|
|
}
|
|
break;
|
|
}
|
|
case OpData::Imm: {
|
|
if (CompressOrUncompress) {
|
|
unsigned Entry = getPredicates(MCOpPredicateMap, MCOpPredicates,
|
|
DestOperand.Rec, StringRef("MCOperandPredicate"));
|
|
CondStream.indent(6)
|
|
<< Namespace + "ValidateMCOperand(" + "MCOperand::createImm(" +
|
|
std::to_string(DestOperandMap[OpNo].Data.Imm) + "), STI, " +
|
|
std::to_string(Entry) + ") &&\n";
|
|
} else {
|
|
unsigned Entry = getPredicates(ImmLeafPredicateMap, ImmLeafPredicates,
|
|
DestOperand.Rec, StringRef("ImmediateCode"));
|
|
CondStream.indent(6)
|
|
<< Namespace + "ValidateMachineOperand(" + "MachineOperand::CreateImm(" +
|
|
std::to_string(DestOperandMap[OpNo].Data.Imm) + "), SubTarget, " +
|
|
std::to_string(Entry) + ") &&\n";
|
|
}
|
|
if (CompressOrUncompress)
|
|
CodeStream.indent(6)
|
|
<< "OutInst.addOperand(MCOperand::createImm(" +
|
|
std::to_string(DestOperandMap[OpNo].Data.Imm) + "));\n";
|
|
} break;
|
|
case OpData::Reg: {
|
|
if (CompressOrUncompress) {
|
|
// Fixed register has been validated at pattern validation time.
|
|
Record *Reg = DestOperandMap[OpNo].Data.Reg;
|
|
CodeStream.indent(6) << "OutInst.addOperand(MCOperand::createReg(" +
|
|
Namespace + "::" + Reg->getName().str() +
|
|
"));\n";
|
|
}
|
|
} break;
|
|
}
|
|
++OpNo;
|
|
}
|
|
if (CompressOrUncompress)
|
|
CodeStream.indent(6) << "OutInst.setLoc(MI.getLoc());\n";
|
|
CaseStream << mergeCondAndCode(CondStream, CodeStream);
|
|
PrevOp = CurOp;
|
|
}
|
|
Func << CaseStream.str() << "\n";
|
|
// Close brace for the last case.
|
|
Func.indent(4) << "} // case " + CurOp + "\n";
|
|
Func.indent(2) << "} // switch\n";
|
|
Func.indent(2) << "return false;\n}\n";
|
|
|
|
if (!MCOpPredicates.empty()) {
|
|
o << "static bool " << Namespace
|
|
<< "ValidateMCOperand(const MCOperand &MCOp,\n"
|
|
<< " const MCSubtargetInfo &STI,\n"
|
|
<< " unsigned PredicateIndex) {\n"
|
|
<< " switch (PredicateIndex) {\n"
|
|
<< " default:\n"
|
|
<< " llvm_unreachable(\"Unknown MCOperandPredicate kind\");\n"
|
|
<< " break;\n";
|
|
|
|
printPredicates(MCOpPredicates, "MCOperandPredicate", o);
|
|
|
|
o << " }\n"
|
|
<< "}\n\n";
|
|
}
|
|
|
|
if (!ImmLeafPredicates.empty()) {
|
|
o << "static bool " << Namespace
|
|
<< "ValidateMachineOperand(const MachineOperand &MO,\n"
|
|
<< " const RISCVSubtarget *Subtarget,\n"
|
|
<< " unsigned PredicateIndex) {\n"
|
|
<< " int64_t Imm = MO.getImm(); \n"
|
|
<< " switch (PredicateIndex) {\n"
|
|
<< " default:\n"
|
|
<< " llvm_unreachable(\"Unknown ImmLeaf Predicate kind\");\n"
|
|
<< " break;\n";
|
|
|
|
printPredicates(ImmLeafPredicates, "ImmediateCode", o);
|
|
|
|
o << " }\n"
|
|
<< "}\n\n";
|
|
}
|
|
|
|
o << FuncH.str();
|
|
if (NeedMRI && EType == EmitterType::Compress)
|
|
o.indent(2) << "const MCRegisterInfo &MRI = *Context.getRegisterInfo();\n";
|
|
o << Func.str();
|
|
|
|
if (EType == EmitterType::Compress)
|
|
o << "\n#endif //GEN_COMPRESS_INSTR\n";
|
|
else if (EType == EmitterType::Uncompress)
|
|
o << "\n#endif //GEN_UNCOMPRESS_INSTR\n\n";
|
|
else if (EType == EmitterType::CheckCompress)
|
|
o << "\n#endif //GEN_CHECK_COMPRESS_INSTR\n\n";
|
|
}
|
|
|
|
void RISCVCompressInstEmitter::run(raw_ostream &o) {
|
|
Record *CompressClass = Records.getClass("CompressPat");
|
|
assert(CompressClass && "Compress class definition missing!");
|
|
std::vector<Record *> Insts;
|
|
for (const auto &D : Records.getDefs()) {
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if (D.second->isSubClassOf(CompressClass))
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Insts.push_back(D.second.get());
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}
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// Process the CompressPat definitions, validating them as we do so.
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for (unsigned i = 0, e = Insts.size(); i != e; ++i)
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evaluateCompressPat(Insts[i]);
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// Emit file header.
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emitSourceFileHeader("Compress instruction Source Fragment", o);
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// Generate compressInst() function.
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emitCompressInstEmitter(o, EmitterType::Compress);
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// Generate uncompressInst() function.
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emitCompressInstEmitter(o, EmitterType::Uncompress);
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// Generate isCompressibleInst() function.
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emitCompressInstEmitter(o, EmitterType::CheckCompress);
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}
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namespace llvm {
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void EmitCompressInst(RecordKeeper &RK, raw_ostream &OS) {
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RISCVCompressInstEmitter(RK).run(OS);
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}
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} // namespace llvm
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