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31783d0fe9
Summary: This patch enables the following 1. AMD family 17h architecture using "znver1" tune flag (-march, -mcpu). 2. ISAs that are enabled for "znver1" architecture. 3. Checks ADX isa from cpuid to identify "znver1" flag when -march=native is used. 4. ISAs FMA4, XOP are disabled as they are dropped from amdfam17. 5. For the time being, it uses the btver2 scheduler model. 6. Test file is updated to check this flag. This item is linked to clang review item https://reviews.llvm.org/D28018 Patch by Ganesh Gopalasubramanian Reviewers: RKSimon, craig.topper Subscribers: vprasad, RKSimon, ashutosh.nema, llvm-commits Differential Revision: https://reviews.llvm.org/D28017 llvm-svn: 291543
344 lines
11 KiB
LLVM
344 lines
11 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; Test patterns which generates lzcnt instructions.
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; Eg: zext(or(setcc(cmp), setcc(cmp))) -> shr(or(lzcnt, lzcnt))
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; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=btver2 | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=btver2 -mattr=-fast-lzcnt | FileCheck --check-prefix=NOFASTLZCNT %s
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; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=znver1 | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=znver1 -mattr=-fast-lzcnt | FileCheck --check-prefix=NOFASTLZCNT %s
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; Test one 32-bit input, output is 32-bit, no transformations expected.
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define i32 @test_zext_cmp0(i32 %a) {
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; CHECK-LABEL: test_zext_cmp0:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: testl %edi, %edi
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: retq
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;
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; NOFASTLZCNT-LABEL: test_zext_cmp0:
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; NOFASTLZCNT: # BB#0: # %entry
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; NOFASTLZCNT-NEXT: xorl %eax, %eax
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; NOFASTLZCNT-NEXT: testl %edi, %edi
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; NOFASTLZCNT-NEXT: sete %al
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; NOFASTLZCNT-NEXT: retq
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entry:
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%cmp = icmp eq i32 %a, 0
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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; Test two 32-bit inputs, output is 32-bit.
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define i32 @test_zext_cmp1(i32 %a, i32 %b) {
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; CHECK-LABEL: test_zext_cmp1:
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; CHECK: # BB#0:
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; CHECK-NEXT: lzcntl %edi, %ecx
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; CHECK-NEXT: lzcntl %esi, %eax
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; CHECK-NEXT: orl %ecx, %eax
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; CHECK-NEXT: shrl $5, %eax
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; CHECK-NEXT: retq
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;
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; NOFASTLZCNT-LABEL: test_zext_cmp1:
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; NOFASTLZCNT: # BB#0:
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; NOFASTLZCNT-NEXT: testl %edi, %edi
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; NOFASTLZCNT-NEXT: sete %al
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; NOFASTLZCNT-NEXT: testl %esi, %esi
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; NOFASTLZCNT-NEXT: sete %cl
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; NOFASTLZCNT-NEXT: orb %al, %cl
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; NOFASTLZCNT-NEXT: movzbl %cl, %eax
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; NOFASTLZCNT-NEXT: retq
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%cmp = icmp eq i32 %a, 0
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%cmp1 = icmp eq i32 %b, 0
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%or = or i1 %cmp, %cmp1
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%lor.ext = zext i1 %or to i32
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ret i32 %lor.ext
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}
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; Test two 64-bit inputs, output is 64-bit.
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define i64 @test_zext_cmp2(i64 %a, i64 %b) {
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; CHECK-LABEL: test_zext_cmp2:
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; CHECK: # BB#0:
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; CHECK-NEXT: lzcntq %rdi, %rcx
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; CHECK-NEXT: lzcntq %rsi, %rax
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; CHECK-NEXT: orl %ecx, %eax
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; CHECK-NEXT: shrl $6, %eax
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; CHECK-NEXT: retq
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;
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; NOFASTLZCNT-LABEL: test_zext_cmp2:
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; NOFASTLZCNT: # BB#0:
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; NOFASTLZCNT-NEXT: testq %rdi, %rdi
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; NOFASTLZCNT-NEXT: sete %al
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; NOFASTLZCNT-NEXT: testq %rsi, %rsi
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; NOFASTLZCNT-NEXT: sete %cl
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; NOFASTLZCNT-NEXT: orb %al, %cl
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; NOFASTLZCNT-NEXT: movzbl %cl, %eax
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; NOFASTLZCNT-NEXT: retq
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%cmp = icmp eq i64 %a, 0
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%cmp1 = icmp eq i64 %b, 0
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%or = or i1 %cmp, %cmp1
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%lor.ext = zext i1 %or to i64
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ret i64 %lor.ext
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}
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; Test two 16-bit inputs, output is 16-bit.
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; The transform is disabled for the 16-bit case, as we still have to clear the
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; upper 16-bits, adding one more instruction.
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define i16 @test_zext_cmp3(i16 %a, i16 %b) {
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; CHECK-LABEL: test_zext_cmp3:
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; CHECK: # BB#0:
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; CHECK-NEXT: testw %di, %di
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: testw %si, %si
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; CHECK-NEXT: sete %cl
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; CHECK-NEXT: orb %al, %cl
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; CHECK-NEXT: movzbl %cl, %eax
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; CHECK-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
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; CHECK-NEXT: retq
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;
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; NOFASTLZCNT-LABEL: test_zext_cmp3:
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; NOFASTLZCNT: # BB#0:
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; NOFASTLZCNT-NEXT: testw %di, %di
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; NOFASTLZCNT-NEXT: sete %al
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; NOFASTLZCNT-NEXT: testw %si, %si
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; NOFASTLZCNT-NEXT: sete %cl
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; NOFASTLZCNT-NEXT: orb %al, %cl
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; NOFASTLZCNT-NEXT: movzbl %cl, %eax
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; NOFASTLZCNT-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
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; NOFASTLZCNT-NEXT: retq
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%cmp = icmp eq i16 %a, 0
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%cmp1 = icmp eq i16 %b, 0
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%or = or i1 %cmp, %cmp1
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%lor.ext = zext i1 %or to i16
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ret i16 %lor.ext
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}
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; Test two 32-bit inputs, output is 64-bit.
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define i64 @test_zext_cmp4(i32 %a, i32 %b) {
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; CHECK-LABEL: test_zext_cmp4:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: lzcntl %edi, %ecx
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; CHECK-NEXT: lzcntl %esi, %eax
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; CHECK-NEXT: orl %ecx, %eax
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; CHECK-NEXT: shrl $5, %eax
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; CHECK-NEXT: retq
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;
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; NOFASTLZCNT-LABEL: test_zext_cmp4:
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; NOFASTLZCNT: # BB#0: # %entry
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; NOFASTLZCNT-NEXT: testl %edi, %edi
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; NOFASTLZCNT-NEXT: sete %al
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; NOFASTLZCNT-NEXT: testl %esi, %esi
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; NOFASTLZCNT-NEXT: sete %cl
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; NOFASTLZCNT-NEXT: orb %al, %cl
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; NOFASTLZCNT-NEXT: movzbl %cl, %eax
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; NOFASTLZCNT-NEXT: retq
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entry:
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%cmp = icmp eq i32 %a, 0
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%cmp1 = icmp eq i32 %b, 0
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%0 = or i1 %cmp, %cmp1
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%conv = zext i1 %0 to i64
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ret i64 %conv
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}
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; Test two 64-bit inputs, output is 32-bit.
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define i32 @test_zext_cmp5(i64 %a, i64 %b) {
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; CHECK-LABEL: test_zext_cmp5:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: lzcntq %rdi, %rcx
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; CHECK-NEXT: lzcntq %rsi, %rax
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; CHECK-NEXT: orl %ecx, %eax
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; CHECK-NEXT: shrl $6, %eax
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; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill>
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; CHECK-NEXT: retq
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;
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; NOFASTLZCNT-LABEL: test_zext_cmp5:
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; NOFASTLZCNT: # BB#0: # %entry
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; NOFASTLZCNT-NEXT: testq %rdi, %rdi
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; NOFASTLZCNT-NEXT: sete %al
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; NOFASTLZCNT-NEXT: testq %rsi, %rsi
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; NOFASTLZCNT-NEXT: sete %cl
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; NOFASTLZCNT-NEXT: orb %al, %cl
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; NOFASTLZCNT-NEXT: movzbl %cl, %eax
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; NOFASTLZCNT-NEXT: retq
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entry:
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%cmp = icmp eq i64 %a, 0
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%cmp1 = icmp eq i64 %b, 0
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%0 = or i1 %cmp, %cmp1
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%lor.ext = zext i1 %0 to i32
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ret i32 %lor.ext
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}
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; Test three 32-bit inputs, output is 32-bit.
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define i32 @test_zext_cmp6(i32 %a, i32 %b, i32 %c) {
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; CHECK-LABEL: test_zext_cmp6:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: lzcntl %edi, %eax
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; CHECK-NEXT: lzcntl %esi, %ecx
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; CHECK-NEXT: orl %eax, %ecx
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; CHECK-NEXT: lzcntl %edx, %eax
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; CHECK-NEXT: orl %ecx, %eax
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; CHECK-NEXT: shrl $5, %eax
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; CHECK-NEXT: retq
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;
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; NOFASTLZCNT-LABEL: test_zext_cmp6:
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; NOFASTLZCNT: # BB#0: # %entry
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; NOFASTLZCNT-NEXT: testl %edi, %edi
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; NOFASTLZCNT-NEXT: sete %al
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; NOFASTLZCNT-NEXT: testl %esi, %esi
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; NOFASTLZCNT-NEXT: sete %cl
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; NOFASTLZCNT-NEXT: orb %al, %cl
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; NOFASTLZCNT-NEXT: testl %edx, %edx
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; NOFASTLZCNT-NEXT: sete %al
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; NOFASTLZCNT-NEXT: orb %cl, %al
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; NOFASTLZCNT-NEXT: movzbl %al, %eax
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; NOFASTLZCNT-NEXT: retq
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entry:
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%cmp = icmp eq i32 %a, 0
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%cmp1 = icmp eq i32 %b, 0
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%or.cond = or i1 %cmp, %cmp1
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%cmp2 = icmp eq i32 %c, 0
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%.cmp2 = or i1 %or.cond, %cmp2
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%lor.ext = zext i1 %.cmp2 to i32
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ret i32 %lor.ext
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}
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; Test three 32-bit inputs, output is 32-bit, but compared to test_zext_cmp6 test,
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; %.cmp2 inputs' order is inverted.
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define i32 @test_zext_cmp7(i32 %a, i32 %b, i32 %c) {
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; CHECK-LABEL: test_zext_cmp7:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: lzcntl %edi, %eax
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; CHECK-NEXT: lzcntl %esi, %ecx
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; CHECK-NEXT: orl %eax, %ecx
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; CHECK-NEXT: lzcntl %edx, %eax
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; CHECK-NEXT: orl %ecx, %eax
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; CHECK-NEXT: shrl $5, %eax
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; CHECK-NEXT: retq
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;
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; NOFASTLZCNT-LABEL: test_zext_cmp7:
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; NOFASTLZCNT: # BB#0: # %entry
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; NOFASTLZCNT-NEXT: testl %edi, %edi
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; NOFASTLZCNT-NEXT: sete %al
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; NOFASTLZCNT-NEXT: testl %esi, %esi
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; NOFASTLZCNT-NEXT: sete %cl
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; NOFASTLZCNT-NEXT: orb %al, %cl
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; NOFASTLZCNT-NEXT: testl %edx, %edx
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; NOFASTLZCNT-NEXT: sete %al
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; NOFASTLZCNT-NEXT: orb %cl, %al
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; NOFASTLZCNT-NEXT: movzbl %al, %eax
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; NOFASTLZCNT-NEXT: retq
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entry:
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%cmp = icmp eq i32 %a, 0
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%cmp1 = icmp eq i32 %b, 0
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%or.cond = or i1 %cmp, %cmp1
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%cmp2 = icmp eq i32 %c, 0
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%.cmp2 = or i1 %cmp2, %or.cond
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%lor.ext = zext i1 %.cmp2 to i32
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ret i32 %lor.ext
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}
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; Test four 32-bit inputs, output is 32-bit.
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define i32 @test_zext_cmp8(i32 %a, i32 %b, i32 %c, i32 %d) {
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; CHECK-LABEL: test_zext_cmp8:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: lzcntl %edi, %eax
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; CHECK-NEXT: lzcntl %esi, %esi
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; CHECK-NEXT: lzcntl %edx, %edx
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; CHECK-NEXT: orl %eax, %esi
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; CHECK-NEXT: lzcntl %ecx, %eax
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; CHECK-NEXT: orl %edx, %eax
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; CHECK-NEXT: orl %esi, %eax
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; CHECK-NEXT: shrl $5, %eax
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; CHECK-NEXT: retq
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;
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; NOFASTLZCNT-LABEL: test_zext_cmp8:
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; NOFASTLZCNT: # BB#0: # %entry
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; NOFASTLZCNT-NEXT: testl %edi, %edi
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; NOFASTLZCNT-NEXT: sete %dil
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; NOFASTLZCNT-NEXT: testl %esi, %esi
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; NOFASTLZCNT-NEXT: sete %al
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; NOFASTLZCNT-NEXT: orb %dil, %al
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; NOFASTLZCNT-NEXT: testl %edx, %edx
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; NOFASTLZCNT-NEXT: sete %dl
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; NOFASTLZCNT-NEXT: testl %ecx, %ecx
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; NOFASTLZCNT-NEXT: sete %cl
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; NOFASTLZCNT-NEXT: orb %dl, %cl
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; NOFASTLZCNT-NEXT: orb %al, %cl
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; NOFASTLZCNT-NEXT: movzbl %cl, %eax
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; NOFASTLZCNT-NEXT: retq
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entry:
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%cmp = icmp eq i32 %a, 0
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%cmp1 = icmp eq i32 %b, 0
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%or.cond = or i1 %cmp, %cmp1
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%cmp3 = icmp eq i32 %c, 0
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%or.cond5 = or i1 %or.cond, %cmp3
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%cmp4 = icmp eq i32 %d, 0
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%.cmp4 = or i1 %or.cond5, %cmp4
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%lor.ext = zext i1 %.cmp4 to i32
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ret i32 %lor.ext
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}
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; Test one 32-bit input, one 64-bit input, output is 32-bit.
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define i32 @test_zext_cmp9(i32 %a, i64 %b) {
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; CHECK-LABEL: test_zext_cmp9:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: lzcntq %rsi, %rax
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; CHECK-NEXT: lzcntl %edi, %ecx
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; CHECK-NEXT: shrl $5, %ecx
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; CHECK-NEXT: shrl $6, %eax
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; CHECK-NEXT: orl %ecx, %eax
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; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill>
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; CHECK-NEXT: retq
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;
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; NOFASTLZCNT-LABEL: test_zext_cmp9:
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; NOFASTLZCNT: # BB#0: # %entry
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; NOFASTLZCNT-NEXT: testl %edi, %edi
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; NOFASTLZCNT-NEXT: sete %al
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; NOFASTLZCNT-NEXT: testq %rsi, %rsi
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; NOFASTLZCNT-NEXT: sete %cl
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; NOFASTLZCNT-NEXT: orb %al, %cl
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; NOFASTLZCNT-NEXT: movzbl %cl, %eax
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; NOFASTLZCNT-NEXT: retq
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entry:
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%cmp = icmp eq i32 %a, 0
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%cmp1 = icmp eq i64 %b, 0
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%0 = or i1 %cmp, %cmp1
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%lor.ext = zext i1 %0 to i32
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ret i32 %lor.ext
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}
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; Test 2 128-bit inputs, output is 32-bit, no transformations expected.
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define i32 @test_zext_cmp10(i64 %a.coerce0, i64 %a.coerce1, i64 %b.coerce0, i64 %b.coerce1) {
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; CHECK-LABEL: test_zext_cmp10:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: orq %rsi, %rdi
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: orq %rcx, %rdx
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; CHECK-NEXT: sete %cl
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; CHECK-NEXT: orb %al, %cl
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; CHECK-NEXT: movzbl %cl, %eax
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; CHECK-NEXT: retq
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;
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; NOFASTLZCNT-LABEL: test_zext_cmp10:
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; NOFASTLZCNT: # BB#0: # %entry
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; NOFASTLZCNT-NEXT: orq %rsi, %rdi
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; NOFASTLZCNT-NEXT: sete %al
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; NOFASTLZCNT-NEXT: orq %rcx, %rdx
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; NOFASTLZCNT-NEXT: sete %cl
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; NOFASTLZCNT-NEXT: orb %al, %cl
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; NOFASTLZCNT-NEXT: movzbl %cl, %eax
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; NOFASTLZCNT-NEXT: retq
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entry:
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%a.sroa.2.0.insert.ext = zext i64 %a.coerce1 to i128
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%a.sroa.2.0.insert.shift = shl nuw i128 %a.sroa.2.0.insert.ext, 64
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%a.sroa.0.0.insert.ext = zext i64 %a.coerce0 to i128
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%a.sroa.0.0.insert.insert = or i128 %a.sroa.2.0.insert.shift, %a.sroa.0.0.insert.ext
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%b.sroa.2.0.insert.ext = zext i64 %b.coerce1 to i128
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%b.sroa.2.0.insert.shift = shl nuw i128 %b.sroa.2.0.insert.ext, 64
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%b.sroa.0.0.insert.ext = zext i64 %b.coerce0 to i128
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%b.sroa.0.0.insert.insert = or i128 %b.sroa.2.0.insert.shift, %b.sroa.0.0.insert.ext
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%cmp = icmp eq i128 %a.sroa.0.0.insert.insert, 0
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%cmp3 = icmp eq i128 %b.sroa.0.0.insert.insert, 0
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%0 = or i1 %cmp, %cmp3
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%lor.ext = zext i1 %0 to i32
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ret i32 %lor.ext
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}
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