Craig Topper 0a8fb0b4d7 [RISCV] Custom lower (i32 (fptoui/fptosi X)). ... I stumbled onto a case where our (sext_inreg (assertzexti32 (fptoui X)), i32) isel pattern can cause an fcvt.wu and fcvt.lu to be emitted if the assertzexti32 has an additional user. If we add a one use check it would just cause a fcvt.lu followed by a sext.w when only need a fcvt.wu to satisfy both users. To mitigate this I've added custom isel and new ISD opcodes for fcvt.wu. This allows us to keep know it started life as a conversion to i32 without needing to match multiple nodes. ComputeNumSignBits has been taught that this new nodes produces 33 sign bits. To prevent regressions when we need to zero extend the result of an (i32 (fptoui X)), I've added a DAG combine to convert it to an (i64 (fptoui X)) before type legalization. In most cases this would happen in InstCombine, but a zero_extend can be created for function returns or arguments. To keep everything consistent I've added new nodes for fptosi as well. Reviewed By: luismarques Differential Revision: https://reviews.llvm.org/D106346		2021-07-24 10:50:43 -07:00
..
AsmParser	[RISCV] Teach constant materialization that it can use zext.w at the end with Zba to reduce number of instructions.	2021-07-16 09:35:56 -07:00
Disassembler
MCTargetDesc	[RISCV] Teach RISCVMatInt about cases where it can use LUI+SLLI to replace LUI+ADDI+SLLI for large constants.	2021-07-20 09:22:06 -07:00
TargetInfo
CMakeLists.txt
RISCV.h
RISCV.td
RISCVAsmPrinter.cpp
RISCVCallingConv.td
RISCVCallLowering.cpp
RISCVCallLowering.h
RISCVExpandAtomicPseudoInsts.cpp
RISCVExpandPseudoInsts.cpp
RISCVFrameLowering.cpp	[RISCV] Add FrameSetup/FrameDestroy flag to prologue/epilog instructions.	2021-07-23 11:35:19 +08:00
RISCVFrameLowering.h	[RISCV] Add FrameSetup/FrameDestroy flag to prologue/epilog instructions.	2021-07-23 11:35:19 +08:00
RISCVInsertVSETVLI.cpp	[RISCV] Avoid using x0,x0 vsetvli for vmv.x.s and vfmv.f.s unless we know the sew/lmul ratio is constant.	2021-07-23 09:12:05 -07:00
RISCVInstrFormats.td
RISCVInstrFormatsC.td
RISCVInstrFormatsV.td
RISCVInstrInfo.cpp	[RISCV] Add FrameSetup/FrameDestroy flag to prologue/epilog instructions.	2021-07-23 11:35:19 +08:00
RISCVInstrInfo.h	[RISCV] Add FrameSetup/FrameDestroy flag to prologue/epilog instructions.	2021-07-23 11:35:19 +08:00
RISCVInstrInfo.td	[RISCV] Add custom isel to select (and (srl X, C1), C2) and (and (shl X, C1), C2)	2021-07-20 08:53:55 -07:00
RISCVInstrInfoA.td
RISCVInstrInfoB.td	[RISCV] Optimize multiplication in the zba extension with SH*ADD	2021-07-22 10:28:41 +08:00
RISCVInstrInfoC.td
RISCVInstrInfoD.td	[RISCV] Custom lower (i32 (fptoui/fptosi X)).	2021-07-24 10:50:43 -07:00
RISCVInstrInfoF.td	[RISCV] Custom lower (i32 (fptoui/fptosi X)).	2021-07-24 10:50:43 -07:00
RISCVInstrInfoM.td
RISCVInstrInfoV.td
RISCVInstrInfoVPseudos.td	[RISCV] Use tail agnostic policy for fixed vector vwmacc(u).	2021-07-16 10:41:09 -07:00
RISCVInstrInfoVSDPatterns.td	[RISCV] Add isel patterns to match vmacc/vmadd/vnmsub/vnmsac from add/sub and mul.	2021-06-21 11:27:44 -07:00
RISCVInstrInfoVVLPatterns.td	[RISCV] Use tail agnostic policy for fixed vector vwmacc(u).	2021-07-16 10:41:09 -07:00
RISCVInstrInfoZfh.td	[RISCV] Custom lower (i32 (fptoui/fptosi X)).	2021-07-24 10:50:43 -07:00
RISCVInstructionSelector.cpp
RISCVISelDAGToDAG.cpp	[RISCV] Add custom isel to select (and (srl X, C1), C2) and (and (shl X, C1), C2)	2021-07-20 08:53:55 -07:00
RISCVISelDAGToDAG.h	[RISCV] Add custom isel to select (and (srl X, C1), C2) and (and (shl X, C1), C2)	2021-07-20 08:53:55 -07:00
RISCVISelLowering.cpp	[RISCV] Custom lower (i32 (fptoui/fptosi X)).	2021-07-24 10:50:43 -07:00
RISCVISelLowering.h	[RISCV] Custom lower (i32 (fptoui/fptosi X)).	2021-07-24 10:50:43 -07:00
RISCVLegalizerInfo.cpp	[globalisel][legalizer] Separate the deprecated LegalizerInfo from the current one	2021-06-01 13:23:48 -07:00
RISCVLegalizerInfo.h
RISCVMachineFunctionInfo.h
RISCVMCInstLower.cpp
RISCVMergeBaseOffset.cpp
RISCVRegisterBankInfo.cpp
RISCVRegisterBankInfo.h
RISCVRegisterBanks.td
RISCVRegisterInfo.cpp	[RISCV] Reserve an emergency spill slot for any RVV spills	2021-06-03 10:44:34 +01:00
RISCVRegisterInfo.h
RISCVRegisterInfo.td	[RISCV] Make VLEN no greater than 65536	2021-07-17 12:47:46 +08:00
RISCVSchedRocket.td
RISCVSchedSiFive7.td
RISCVSchedule.td
RISCVScheduleB.td
RISCVSubtarget.cpp	[RISCV] Make VLEN no greater than 65536	2021-07-17 12:47:46 +08:00
RISCVSubtarget.h	[RISCV] Don't enable loop vectorizer interleaving if the V extension isn't enabled.	2021-06-07 10:20:59 -07:00
RISCVSystemOperands.td
RISCVTargetMachine.cpp
RISCVTargetMachine.h
RISCVTargetObjectFile.cpp
RISCVTargetObjectFile.h
RISCVTargetTransformInfo.cpp	[RISCV] Teach constant materialization that it can use zext.w at the end with Zba to reduce number of instructions.	2021-07-16 09:35:56 -07:00
RISCVTargetTransformInfo.h	[RISCV] Don't enable Interleaved Access Vectorization	2021-06-18 12:32:30 +08:00