Jina Nahias b0f12aa95c [x86] Lowering Mask Set1 intrinsics to LLVM IR ...

This patch, together with a matching clang patch (https://reviews.llvm.org/D37668), implements the lowering of X86 mask set1 intrinsics to IR.

Differential Revision: https://reviews.llvm.org/D37669

llvm-svn: 313625

2017-09-19 11:03:06 +00:00

..

AArch64

[LoopVectorizer] Add more testcases for PR33804.

2017-09-18 17:28:15 +00:00

AMDGPU

AMDGPU: Run internalize symbols at -O0

2017-09-19 07:40:11 +00:00

ARC

[ARC] Add ARC backend.

2017-08-24 15:40:33 +00:00

ARM

[ARM] Use ADDCARRY / SUBCARRY

2017-09-19 09:05:39 +00:00

AVR

[AVR] Enable the '__do_copy_data' function

2017-09-11 10:32:51 +00:00

BPF

bpf: add inline-asm support

2017-09-18 23:29:36 +00:00

Generic

[MIParser] Ensure getHexUint doesn't produce APInts with a bitwidth of 0

2017-09-01 22:17:14 +00:00

Hexagon

[IfConversion] More simple, correct dead/kill liveness handling

2017-09-14 15:53:11 +00:00

Inputs

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Lanai

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Mips

[mips] Pick the right variant of DINS upfront and enable target instruction verification

2017-09-14 10:58:00 +00:00

MIR

AMDGPU: Handle non-temporal loads and stores

2017-09-07 17:14:54 +00:00

MSP430

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Nios2

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NVPTX

[CUDA] Added rudimentary support for CUDA-9 and sm_70.

2017-09-07 18:14:32 +00:00

PowerPC

[XRay][CodeGen] Use the current function symbol as the associated symbol for the instrumentation map

2017-09-14 07:08:23 +00:00

SPARC

Revert "Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding""

2017-09-04 15:47:00 +00:00

SystemZ

Move llvm/test/CodeGen/X86/clear-liverange-spillreg.mir to SystemZ. It was in wrong place.

2017-09-14 00:03:23 +00:00

Thumb

Revert "Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding""

2017-09-04 15:47:00 +00:00

Thumb2

[ARM] Call setBooleanContents(ZeroOrOneBooleanContent)

2017-08-22 11:02:37 +00:00

WebAssembly

[WebAssembly] Add sign extend instructions from atomics proposal

2017-09-13 00:29:06 +00:00

WinEH

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X86

[x86] Lowering Mask Set1 intrinsics to LLVM IR

2017-09-19 11:03:06 +00:00

XCore

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