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https://github.com/RPCS3/llvm-mirror.git
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4de4faa425
Summary: This *might* be the last fold for `sink-addsub-of-const.ll`, but i'm not sure yet. As far as i can tell, there are no regressions here (ignoring x86-32), all changes are either good or neutral. This, almost surprisingly to me, fixes the motivational tests (in `shift-amount-mod.ll`) `@reg32_lshr_by_sub_from_negated` from [[ https://bugs.llvm.org/show_bug.cgi?id=41952 | PR41952 ]]. https://rise4fun.com/Alive/vMd3 Reviewers: RKSimon, t.p.northover, craig.topper, spatel, efriedma Reviewed By: RKSimon Subscribers: sdardis, javed.absar, arichardson, kristof.beyls, jrtc27, atanasyan, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62774 llvm-svn: 362488
428 lines
12 KiB
LLVM
428 lines
12 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=mipsel-mti-linux-gnu < %s | FileCheck %s -check-prefix=MIPS32
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; RUN: llc -mtriple=mips64el-mti-linux-gnu < %s | FileCheck %s -check-prefix=MIPS64
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define i32 @mul5_32(i32 signext %a) {
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; MIPS32-LABEL: mul5_32:
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; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: sll $1, $4, 2
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: addu $2, $1, $4
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;
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; MIPS64-LABEL: mul5_32:
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; MIPS64: # %bb.0: # %entry
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; MIPS64-NEXT: sll $1, $4, 2
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; MIPS64-NEXT: jr $ra
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; MIPS64-NEXT: addu $2, $1, $4
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entry:
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%mul = mul nsw i32 %a, 5
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ret i32 %mul
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}
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define i32 @mul27_32(i32 signext %a) {
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; MIPS32-LABEL: mul27_32:
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; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: sll $1, $4, 2
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; MIPS32-NEXT: addu $1, $1, $4
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; MIPS32-NEXT: sll $2, $4, 5
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: subu $2, $2, $1
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;
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; MIPS64-LABEL: mul27_32:
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; MIPS64: # %bb.0: # %entry
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; MIPS64-NEXT: sll $1, $4, 2
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; MIPS64-NEXT: addu $1, $1, $4
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; MIPS64-NEXT: sll $2, $4, 5
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; MIPS64-NEXT: jr $ra
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; MIPS64-NEXT: subu $2, $2, $1
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entry:
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%mul = mul nsw i32 %a, 27
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ret i32 %mul
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}
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define i32 @muln2147483643_32(i32 signext %a) {
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; MIPS32-LABEL: muln2147483643_32:
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; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: sll $1, $4, 2
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; MIPS32-NEXT: addu $1, $1, $4
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; MIPS32-NEXT: sll $2, $4, 31
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: addu $2, $2, $1
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;
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; MIPS64-LABEL: muln2147483643_32:
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; MIPS64: # %bb.0: # %entry
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; MIPS64-NEXT: sll $1, $4, 2
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; MIPS64-NEXT: addu $1, $1, $4
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; MIPS64-NEXT: sll $2, $4, 31
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; MIPS64-NEXT: jr $ra
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; MIPS64-NEXT: addu $2, $2, $1
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entry:
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%mul = mul nsw i32 %a, -2147483643
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ret i32 %mul
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}
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define i64 @muln9223372036854775805_64(i64 signext %a) {
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; MIPS32-LABEL: muln9223372036854775805_64:
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; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: sll $1, $4, 1
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; MIPS32-NEXT: addu $2, $1, $4
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; MIPS32-NEXT: sltu $1, $2, $1
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; MIPS32-NEXT: srl $3, $4, 31
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; MIPS32-NEXT: sll $6, $5, 1
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; MIPS32-NEXT: or $3, $6, $3
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; MIPS32-NEXT: addu $3, $3, $5
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; MIPS32-NEXT: addu $1, $3, $1
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; MIPS32-NEXT: sll $3, $4, 31
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: addu $3, $3, $1
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;
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; MIPS64-LABEL: muln9223372036854775805_64:
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; MIPS64: # %bb.0: # %entry
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; MIPS64-NEXT: dsll $1, $4, 1
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; MIPS64-NEXT: daddu $1, $1, $4
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; MIPS64-NEXT: dsll $2, $4, 63
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; MIPS64-NEXT: jr $ra
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; MIPS64-NEXT: daddu $2, $2, $1
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entry:
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%mul = mul nsw i64 %a, -9223372036854775805
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ret i64 %mul
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}
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define i128 @muln170141183460469231731687303715884105725_128(i128 signext %a) {
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; MIPS32-LABEL: muln170141183460469231731687303715884105725_128:
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; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: sll $1, $4, 1
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; MIPS32-NEXT: addu $2, $1, $4
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; MIPS32-NEXT: sltu $1, $2, $1
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; MIPS32-NEXT: srl $3, $4, 31
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; MIPS32-NEXT: sll $8, $5, 1
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; MIPS32-NEXT: or $8, $8, $3
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; MIPS32-NEXT: addu $3, $8, $5
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; MIPS32-NEXT: addu $3, $3, $1
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; MIPS32-NEXT: sltu $9, $3, $8
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; MIPS32-NEXT: xor $8, $3, $8
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; MIPS32-NEXT: movz $9, $1, $8
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; MIPS32-NEXT: srl $1, $5, 31
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; MIPS32-NEXT: sll $5, $6, 1
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; MIPS32-NEXT: or $5, $5, $1
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; MIPS32-NEXT: addu $8, $5, $6
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; MIPS32-NEXT: addu $1, $8, $9
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; MIPS32-NEXT: sltu $5, $8, $5
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; MIPS32-NEXT: srl $6, $6, 31
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; MIPS32-NEXT: sll $9, $7, 1
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; MIPS32-NEXT: or $6, $9, $6
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; MIPS32-NEXT: addu $6, $6, $7
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; MIPS32-NEXT: addu $5, $6, $5
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; MIPS32-NEXT: sll $4, $4, 31
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; MIPS32-NEXT: sltu $6, $1, $8
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; MIPS32-NEXT: addu $5, $5, $6
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; MIPS32-NEXT: addu $5, $4, $5
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: move $4, $1
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;
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; MIPS64-LABEL: muln170141183460469231731687303715884105725_128:
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; MIPS64: # %bb.0: # %entry
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; MIPS64-NEXT: dsrl $1, $4, 63
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; MIPS64-NEXT: dsll $2, $5, 1
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; MIPS64-NEXT: or $1, $2, $1
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; MIPS64-NEXT: daddu $1, $1, $5
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; MIPS64-NEXT: dsll $3, $4, 1
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; MIPS64-NEXT: daddu $2, $3, $4
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; MIPS64-NEXT: sltu $3, $2, $3
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; MIPS64-NEXT: dsll $3, $3, 32
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; MIPS64-NEXT: dsrl $3, $3, 32
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; MIPS64-NEXT: daddu $1, $1, $3
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; MIPS64-NEXT: dsll $3, $4, 63
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; MIPS64-NEXT: jr $ra
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; MIPS64-NEXT: daddu $3, $3, $1
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entry:
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%mul = mul nsw i128 %a, -170141183460469231731687303715884105725
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ret i128 %mul
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}
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define i128 @mul170141183460469231731687303715884105723_128(i128 signext %a) {
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; MIPS32-LABEL: mul170141183460469231731687303715884105723_128:
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; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: sll $1, $4, 2
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; MIPS32-NEXT: addu $2, $1, $4
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; MIPS32-NEXT: sltu $1, $2, $1
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; MIPS32-NEXT: srl $3, $4, 30
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; MIPS32-NEXT: sll $8, $5, 2
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; MIPS32-NEXT: or $3, $8, $3
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; MIPS32-NEXT: addu $8, $3, $5
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; MIPS32-NEXT: addu $8, $8, $1
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; MIPS32-NEXT: sltu $9, $8, $3
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; MIPS32-NEXT: xor $3, $8, $3
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; MIPS32-NEXT: sltu $10, $zero, $8
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; MIPS32-NEXT: sltu $11, $zero, $2
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; MIPS32-NEXT: movz $10, $11, $8
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; MIPS32-NEXT: movz $9, $1, $3
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; MIPS32-NEXT: srl $1, $5, 30
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; MIPS32-NEXT: sll $3, $6, 2
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; MIPS32-NEXT: or $1, $3, $1
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; MIPS32-NEXT: addu $3, $1, $6
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; MIPS32-NEXT: addu $5, $3, $9
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; MIPS32-NEXT: sll $4, $4, 31
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; MIPS32-NEXT: negu $9, $5
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; MIPS32-NEXT: sltu $12, $9, $10
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; MIPS32-NEXT: sltu $13, $5, $3
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; MIPS32-NEXT: sltu $1, $3, $1
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; MIPS32-NEXT: srl $3, $6, 30
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; MIPS32-NEXT: sll $6, $7, 2
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; MIPS32-NEXT: or $3, $6, $3
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; MIPS32-NEXT: addu $3, $3, $7
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; MIPS32-NEXT: addu $1, $3, $1
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; MIPS32-NEXT: addu $1, $1, $13
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; MIPS32-NEXT: subu $1, $4, $1
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; MIPS32-NEXT: sltu $3, $zero, $5
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; MIPS32-NEXT: subu $1, $1, $3
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; MIPS32-NEXT: subu $5, $1, $12
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; MIPS32-NEXT: subu $4, $9, $10
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; MIPS32-NEXT: addu $1, $8, $11
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; MIPS32-NEXT: negu $3, $1
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: negu $2, $2
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;
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; MIPS64-LABEL: mul170141183460469231731687303715884105723_128:
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; MIPS64: # %bb.0: # %entry
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; MIPS64-NEXT: dsrl $1, $4, 62
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; MIPS64-NEXT: dsll $2, $5, 2
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; MIPS64-NEXT: or $1, $2, $1
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; MIPS64-NEXT: daddu $1, $1, $5
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; MIPS64-NEXT: dsll $2, $4, 2
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; MIPS64-NEXT: daddu $5, $2, $4
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; MIPS64-NEXT: sltu $2, $5, $2
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; MIPS64-NEXT: dsll $2, $2, 32
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; MIPS64-NEXT: dsrl $2, $2, 32
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; MIPS64-NEXT: daddu $1, $1, $2
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; MIPS64-NEXT: dsll $2, $4, 63
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; MIPS64-NEXT: dsubu $1, $2, $1
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; MIPS64-NEXT: sltu $2, $zero, $5
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; MIPS64-NEXT: dsll $2, $2, 32
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; MIPS64-NEXT: dsrl $2, $2, 32
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; MIPS64-NEXT: dsubu $3, $1, $2
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; MIPS64-NEXT: jr $ra
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; MIPS64-NEXT: dnegu $2, $5
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entry:
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%mul = mul nsw i128 %a, 170141183460469231731687303715884105723
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ret i128 %mul
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}
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define i32 @mul42949673_32(i32 %a) {
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; MIPS32-LABEL: mul42949673_32:
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; MIPS32: # %bb.0:
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; MIPS32-NEXT: lui $1, 655
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; MIPS32-NEXT: ori $1, $1, 23593
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: mul $2, $4, $1
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;
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; MIPS64-LABEL: mul42949673_32:
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; MIPS64: # %bb.0:
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; MIPS64-NEXT: lui $1, 655
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; MIPS64-NEXT: ori $1, $1, 23593
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; MIPS64-NEXT: sll $2, $4, 0
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; MIPS64-NEXT: jr $ra
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; MIPS64-NEXT: mul $2, $2, $1
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%b = mul i32 %a, 42949673
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ret i32 %b
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}
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define i64 @mul42949673_64(i64 %a) {
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; MIPS32-LABEL: mul42949673_64:
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; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: lui $1, 655
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; MIPS32-NEXT: ori $1, $1, 23593
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; MIPS32-NEXT: multu $4, $1
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; MIPS32-NEXT: mflo $2
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; MIPS32-NEXT: mfhi $3
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; MIPS32-NEXT: mul $1, $5, $1
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: addu $3, $3, $1
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;
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; MIPS64-LABEL: mul42949673_64:
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; MIPS64: # %bb.0: # %entry
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; MIPS64-NEXT: lui $1, 655
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; MIPS64-NEXT: ori $1, $1, 23593
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; MIPS64-NEXT: dmult $4, $1
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; MIPS64-NEXT: jr $ra
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; MIPS64-NEXT: mflo $2
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entry:
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%b = mul i64 %a, 42949673
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ret i64 %b
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}
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define i32 @mul22224078_32(i32 %a) {
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; MIPS32-LABEL: mul22224078_32:
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; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: lui $1, 339
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; MIPS32-NEXT: ori $1, $1, 7374
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: mul $2, $4, $1
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;
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; MIPS64-LABEL: mul22224078_32:
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; MIPS64: # %bb.0: # %entry
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; MIPS64-NEXT: lui $1, 339
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; MIPS64-NEXT: ori $1, $1, 7374
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; MIPS64-NEXT: sll $2, $4, 0
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; MIPS64-NEXT: jr $ra
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; MIPS64-NEXT: mul $2, $2, $1
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entry:
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%b = mul i32 %a, 22224078
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ret i32 %b
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}
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define i64 @mul22224078_64(i64 %a) {
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; MIPS32-LABEL: mul22224078_64:
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; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: lui $1, 339
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; MIPS32-NEXT: ori $1, $1, 7374
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; MIPS32-NEXT: multu $4, $1
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; MIPS32-NEXT: mflo $2
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; MIPS32-NEXT: mfhi $3
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; MIPS32-NEXT: mul $1, $5, $1
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: addu $3, $3, $1
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;
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; MIPS64-LABEL: mul22224078_64:
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; MIPS64: # %bb.0: # %entry
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; MIPS64-NEXT: lui $1, 339
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; MIPS64-NEXT: ori $1, $1, 7374
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; MIPS64-NEXT: dmult $4, $1
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; MIPS64-NEXT: jr $ra
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; MIPS64-NEXT: mflo $2
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entry:
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%b = mul i64 %a, 22224078
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ret i64 %b
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}
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define i32 @mul22245375_32(i32 %a) {
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; MIPS32-LABEL: mul22245375_32:
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; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: lui $1, 339
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; MIPS32-NEXT: ori $1, $1, 28671
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: mul $2, $4, $1
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;
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; MIPS64-LABEL: mul22245375_32:
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; MIPS64: # %bb.0: # %entry
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; MIPS64-NEXT: lui $1, 339
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; MIPS64-NEXT: ori $1, $1, 28671
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; MIPS64-NEXT: sll $2, $4, 0
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; MIPS64-NEXT: jr $ra
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; MIPS64-NEXT: mul $2, $2, $1
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entry:
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%b = mul i32 %a, 22245375
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ret i32 %b
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}
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define i64 @mul22245375_64(i64 %a) {
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; MIPS32-LABEL: mul22245375_64:
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; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: lui $1, 339
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; MIPS32-NEXT: ori $1, $1, 28671
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; MIPS32-NEXT: multu $4, $1
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; MIPS32-NEXT: mflo $2
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; MIPS32-NEXT: mfhi $3
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; MIPS32-NEXT: mul $1, $5, $1
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: addu $3, $3, $1
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;
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; MIPS64-LABEL: mul22245375_64:
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; MIPS64: # %bb.0: # %entry
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; MIPS64-NEXT: lui $1, 339
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; MIPS64-NEXT: ori $1, $1, 28671
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; MIPS64-NEXT: dmult $4, $1
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; MIPS64-NEXT: jr $ra
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; MIPS64-NEXT: mflo $2
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entry:
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%b = mul i64 %a, 22245375
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ret i64 %b
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}
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define i32 @mul25165824_32(i32 %a) {
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; MIPS32-LABEL: mul25165824_32:
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; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: lui $1, 339
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; MIPS32-NEXT: ori $1, $1, 28671
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: mul $2, $4, $1
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;
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; MIPS64-LABEL: mul25165824_32:
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; MIPS64: # %bb.0: # %entry
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; MIPS64-NEXT: lui $1, 339
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; MIPS64-NEXT: ori $1, $1, 28671
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; MIPS64-NEXT: sll $2, $4, 0
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; MIPS64-NEXT: jr $ra
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; MIPS64-NEXT: mul $2, $2, $1
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entry:
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%b = mul i32 %a, 22245375
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ret i32 %b
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}
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define i64 @mul25165824_64(i64 %a) {
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; MIPS32-LABEL: mul25165824_64:
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; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: srl $1, $4, 9
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; MIPS32-NEXT: sll $2, $5, 23
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; MIPS32-NEXT: or $1, $2, $1
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; MIPS32-NEXT: srl $2, $4, 8
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; MIPS32-NEXT: sll $3, $5, 24
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; MIPS32-NEXT: or $2, $3, $2
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; MIPS32-NEXT: addu $1, $2, $1
|
|
; MIPS32-NEXT: sll $2, $4, 23
|
|
; MIPS32-NEXT: sll $3, $4, 24
|
|
; MIPS32-NEXT: addu $2, $3, $2
|
|
; MIPS32-NEXT: sltu $3, $2, $3
|
|
; MIPS32-NEXT: jr $ra
|
|
; MIPS32-NEXT: addu $3, $1, $3
|
|
;
|
|
; MIPS64-LABEL: mul25165824_64:
|
|
; MIPS64: # %bb.0: # %entry
|
|
; MIPS64-NEXT: dsll $1, $4, 23
|
|
; MIPS64-NEXT: dsll $2, $4, 24
|
|
; MIPS64-NEXT: jr $ra
|
|
; MIPS64-NEXT: daddu $2, $2, $1
|
|
entry:
|
|
%b = mul i64 %a, 25165824
|
|
ret i64 %b
|
|
}
|
|
|
|
define i32 @mul33554432_32(i32 %a) {
|
|
; MIPS32-LABEL: mul33554432_32:
|
|
; MIPS32: # %bb.0: # %entry
|
|
; MIPS32-NEXT: lui $1, 339
|
|
; MIPS32-NEXT: ori $1, $1, 28671
|
|
; MIPS32-NEXT: jr $ra
|
|
; MIPS32-NEXT: mul $2, $4, $1
|
|
;
|
|
; MIPS64-LABEL: mul33554432_32:
|
|
; MIPS64: # %bb.0: # %entry
|
|
; MIPS64-NEXT: lui $1, 339
|
|
; MIPS64-NEXT: ori $1, $1, 28671
|
|
; MIPS64-NEXT: sll $2, $4, 0
|
|
; MIPS64-NEXT: jr $ra
|
|
; MIPS64-NEXT: mul $2, $2, $1
|
|
entry:
|
|
%b = mul i32 %a, 22245375
|
|
ret i32 %b
|
|
}
|
|
|
|
define i64 @mul33554432_64(i64 %a) {
|
|
; MIPS32-LABEL: mul33554432_64:
|
|
; MIPS32: # %bb.0: # %entry
|
|
; MIPS32-NEXT: srl $1, $4, 7
|
|
; MIPS32-NEXT: sll $2, $5, 25
|
|
; MIPS32-NEXT: or $3, $2, $1
|
|
; MIPS32-NEXT: jr $ra
|
|
; MIPS32-NEXT: sll $2, $4, 25
|
|
;
|
|
; MIPS64-LABEL: mul33554432_64:
|
|
; MIPS64: # %bb.0: # %entry
|
|
; MIPS64-NEXT: jr $ra
|
|
; MIPS64-NEXT: dsll $2, $4, 25
|
|
entry:
|
|
%b = mul i64 %a, 33554432
|
|
ret i64 %b
|
|
}
|