.. |
AArch64
|
[AArch64] Add isel support for f16 indexed LD/ST.
|
2015-08-04 01:29:38 +00:00 |
AMDGPU
|
AMDGPU/SI: Add implicit register operands in the correct order.
|
2015-07-31 23:30:09 +00:00 |
ARM
|
ARMISelDAGToDAG.cpp had this self-contradictory code:
|
2015-08-05 11:02:14 +00:00 |
BPF
|
[bpf] rename triple names bpf_be -> bpfeb
|
2015-06-05 16:11:14 +00:00 |
CPP
|
|
|
Generic
|
Update test suite to make "ninja check" succeed without native backend builtin
|
2015-08-04 06:32:54 +00:00 |
Hexagon
|
DI: Disallow uniquable DICompileUnits
|
2015-08-03 17:26:41 +00:00 |
Inputs
|
DI: Disallow uniquable DICompileUnits
|
2015-08-03 17:26:41 +00:00 |
Mips
|
Revert r229675 - [mips] Avoid redundant sign extension of the result of binary bitwise instructions.
|
2015-08-04 14:26:35 +00:00 |
MIR
|
MIR Serialization: Serialize the 'non-temporal' machine memory operand flag.
|
2015-08-06 16:49:30 +00:00 |
MSP430
|
|
|
NVPTX
|
[NVPTX] Use LDG for pointer induction variables.
|
2015-08-05 23:11:57 +00:00 |
PowerPC
|
[MachineCombiner] Don't use the opcode-only form of computeInstrLatency
|
2015-08-05 07:45:28 +00:00 |
SPARC
|
[SPARC] Cleanup handling of the Y/ASR registers.
|
2015-07-08 16:25:12 +00:00 |
SystemZ
|
[DAGCombiner] Account for getVectorIdxTy() when narrowing vector load
|
2015-05-05 19:34:10 +00:00 |
Thumb
|
DI: Disallow uniquable DICompileUnits
|
2015-08-03 17:26:41 +00:00 |
Thumb2
|
ARMLoadStoreOptimizer: Create LDRD/STRD on thumb2
|
2015-07-21 00:18:59 +00:00 |
WebAssembly
|
WebAssembly: implement getScalarShiftAmountTy so we can shift by amount, with type
|
2015-08-03 00:00:11 +00:00 |
WinEH
|
[WinEH] Strip the \01 character from the __CxxFrameHandler3 thunk name
|
2015-07-13 17:55:14 +00:00 |
X86
|
[X86] Improve EmitLoweredSelect for contiguous CMOV pseudo instructions.
|
2015-08-06 08:45:34 +00:00 |
XCore
|
DI: Disallow uniquable DICompileUnits
|
2015-08-03 17:26:41 +00:00 |