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https://github.com/RPCS3/llvm-mirror.git
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7b7d569297
Summary: A lot of the pseudo instructions are required because LLVM assumes that all integers of the same size as the pointer size are legal. This means that it will not currently expand 16-bit instructions to their 8-bit variants because it thinks 16-bit types are legal for the operations. This also adds all of the CodeGen tests that required the pass to run. Reviewers: arsenm, kparzysz Subscribers: wdng, mgorny, modocache, llvm-commits Differential Revision: https://reviews.llvm.org/D26577 llvm-svn: 287162
125 lines
3.2 KiB
LLVM
125 lines
3.2 KiB
LLVM
; RUN: llc -mattr=avr6 < %s -march=avr | FileCheck %s
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; Tests atomic operations on AVR
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; CHECK-LABEL: atomic_load8
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; CHECK: in r0, 63
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; CHECK-NEXT: cli
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; CHECK-NEXT: ld [[RR:r[0-9]+]], [[RD:(X|Y|Z)]]
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; CHECK-NEXT: out 63, r0
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define i8 @atomic_load8(i8* %foo) {
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%val = load atomic i8, i8* %foo unordered, align 1
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ret i8 %val
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}
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; CHECK-LABEL: atomic_load_swap8
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; CHECK: call __sync_lock_test_and_set_1
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define i8 @atomic_load_swap8(i8* %foo) {
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%val = atomicrmw xchg i8* %foo, i8 13 seq_cst
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ret i8 %val
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}
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; CHECK-LABEL: atomic_load_cmp_swap8
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; CHECK: call __sync_val_compare_and_swap_1
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define i8 @atomic_load_cmp_swap8(i8* %foo) {
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%val = cmpxchg i8* %foo, i8 5, i8 10 acq_rel monotonic
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%value_loaded = extractvalue { i8, i1 } %val, 0
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ret i8 %value_loaded
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}
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; CHECK-LABEL: atomic_load_add8
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; CHECK: in r0, 63
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; CHECK-NEXT: cli
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; CHECK-NEXT: ld [[RD:r[0-9]+]], [[RR:(X|Y|Z)]]
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; CHECK-NEXT: add [[RD]], [[RR1:r[0-9]+]]
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; CHECK-NEXT: st [[RR]], [[RD]]
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; CHECK-NEXT: out 63, r0
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define i8 @atomic_load_add8(i8* %foo) {
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%val = atomicrmw add i8* %foo, i8 13 seq_cst
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ret i8 %val
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}
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; CHECK-LABEL: atomic_load_sub8
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; CHECK: in r0, 63
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; CHECK-NEXT: cli
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; CHECK-NEXT: ld [[RD:r[0-9]+]], [[RR:(X|Y|Z)]]
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; CHECK-NEXT: sub [[RD]], [[RR1:r[0-9]+]]
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; CHECK-NEXT: st [[RR]], [[RD]]
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; CHECK-NEXT: out 63, r0
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define i8 @atomic_load_sub8(i8* %foo) {
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%val = atomicrmw sub i8* %foo, i8 13 seq_cst
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ret i8 %val
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}
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; CHECK-LABEL: atomic_load_and8
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; CHECK: in r0, 63
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; CHECK-NEXT: cli
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; CHECK-NEXT: ld [[RD:r[0-9]+]], [[RR:(X|Y|Z)]]
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; CHECK-NEXT: and [[RD]], [[RR1:r[0-9]+]]
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; CHECK-NEXT: st [[RR]], [[RD]]
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; CHECK-NEXT: out 63, r0
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define i8 @atomic_load_and8(i8* %foo) {
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%val = atomicrmw and i8* %foo, i8 13 seq_cst
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ret i8 %val
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}
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; CHECK-LABEL: atomic_load_or8
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; CHECK: in r0, 63
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; CHECK-NEXT: cli
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; CHECK-NEXT: ld [[RD:r[0-9]+]], [[RR:(X|Y|Z)]]
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; CHECK-NEXT: or [[RD]], [[RR1:r[0-9]+]]
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; CHECK-NEXT: st [[RR]], [[RD]]
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; CHECK-NEXT: out 63, r0
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define i8 @atomic_load_or8(i8* %foo) {
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%val = atomicrmw or i8* %foo, i8 13 seq_cst
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ret i8 %val
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}
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; CHECK-LABEL: atomic_load_xor8
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; CHECK: in r0, 63
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; CHECK-NEXT: cli
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; CHECK-NEXT: ld [[RD:r[0-9]+]], [[RR:(X|Y|Z)]]
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; CHECK-NEXT: eor [[RD]], [[RR1:r[0-9]+]]
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; CHECK-NEXT: st [[RR]], [[RD]]
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; CHECK-NEXT: out 63, r0
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define i8 @atomic_load_xor8(i8* %foo) {
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%val = atomicrmw xor i8* %foo, i8 13 seq_cst
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ret i8 %val
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}
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; CHECK-LABEL: atomic_load_nand8
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; CHECK: call __sync_fetch_and_nand_1
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define i8 @atomic_load_nand8(i8* %foo) {
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%val = atomicrmw nand i8* %foo, i8 13 seq_cst
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ret i8 %val
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}
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; CHECK-LABEL: atomic_load_max8
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; CHECK: call __sync_fetch_and_max_1
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define i8 @atomic_load_max8(i8* %foo) {
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%val = atomicrmw max i8* %foo, i8 13 seq_cst
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ret i8 %val
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}
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; CHECK-LABEL: atomic_load_min8
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; CHECK: call __sync_fetch_and_min_1
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define i8 @atomic_load_min8(i8* %foo) {
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%val = atomicrmw min i8* %foo, i8 13 seq_cst
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ret i8 %val
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}
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; CHECK-LABEL: atomic_load_umax8
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; CHECK: call __sync_fetch_and_umax_1
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define i8 @atomic_load_umax8(i8* %foo) {
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%val = atomicrmw umax i8* %foo, i8 13 seq_cst
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ret i8 %val
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}
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; CHECK-LABEL: atomic_load_umin8
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; CHECK: call __sync_fetch_and_umin_1
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define i8 @atomic_load_umin8(i8* %foo) {
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%val = atomicrmw umin i8* %foo, i8 13 seq_cst
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ret i8 %val
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}
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