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e768b5aa55
Initial patch adding assembly support for Armv8.4-A. Besides adding v8.4 as a supported architecture to the usual places, this also adds target features for the different crypto algorithms. Armv8.4-A introduced new crypto algorithms, made them optional, and allows different combinations: - none of the v8.4 crypto functions are supported, which is independent of the implementation of the Armv8.0 SHA1 and SHA2 instructions. - the v8.4 SHA512 and SHA3 support is implemented, in this case the Armv8.0 SHA1 and SHA2 instructions must also be implemented. - the v8.4 SM3 and SM4 support is implemented, which is independent of the implementation of the Armv8.0 SHA1 and SHA2 instructions. - all of the v8.4 crypto functions are supported, in this case the Armv8.0 SHA1 and SHA2 instructions must also be implemented. The v8.4 crypto instructions are added to AArch64 only, and not AArch32, and are made optional extensions to Armv8.2-A. The user-facing Clang options will map on these new target features, their naming will be compatible with GCC and added in follow-up patches. The Armv8.4-A instruction sets can be downloaded here: https://developer.arm.com/products/architecture/a-profile/exploration-tools Differential Revision: https://reviews.llvm.org/D48625 llvm-svn: 335953
929 lines
27 KiB
C++
929 lines
27 KiB
C++
//===-- TargetParser - Parser for target features ---------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a target parser to recognise hardware features such as
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// FPU/CPU/ARCH names as well as specific support such as HDIV, etc.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Support/ARMBuildAttributes.h"
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#include "llvm/Support/TargetParser.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/ADT/Twine.h"
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#include <cctype>
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using namespace llvm;
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using namespace ARM;
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using namespace AArch64;
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namespace {
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// List of canonical FPU names (use getFPUSynonym) and which architectural
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// features they correspond to (use getFPUFeatures).
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// FIXME: TableGen this.
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// The entries must appear in the order listed in ARM::FPUKind for correct indexing
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static const struct {
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const char *NameCStr;
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size_t NameLength;
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ARM::FPUKind ID;
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ARM::FPUVersion FPUVersion;
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ARM::NeonSupportLevel NeonSupport;
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ARM::FPURestriction Restriction;
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StringRef getName() const { return StringRef(NameCStr, NameLength); }
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} FPUNames[] = {
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#define ARM_FPU(NAME, KIND, VERSION, NEON_SUPPORT, RESTRICTION) \
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{ NAME, sizeof(NAME) - 1, KIND, VERSION, NEON_SUPPORT, RESTRICTION },
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#include "llvm/Support/ARMTargetParser.def"
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};
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// List of canonical arch names (use getArchSynonym).
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// This table also provides the build attribute fields for CPU arch
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// and Arch ID, according to the Addenda to the ARM ABI, chapters
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// 2.4 and 2.3.5.2 respectively.
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// FIXME: SubArch values were simplified to fit into the expectations
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// of the triples and are not conforming with their official names.
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// Check to see if the expectation should be changed.
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// FIXME: TableGen this.
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template <typename T> struct ArchNames {
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const char *NameCStr;
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size_t NameLength;
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const char *CPUAttrCStr;
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size_t CPUAttrLength;
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const char *SubArchCStr;
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size_t SubArchLength;
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unsigned DefaultFPU;
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unsigned ArchBaseExtensions;
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T ID;
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ARMBuildAttrs::CPUArch ArchAttr; // Arch ID in build attributes.
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StringRef getName() const { return StringRef(NameCStr, NameLength); }
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// CPU class in build attributes.
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StringRef getCPUAttr() const { return StringRef(CPUAttrCStr, CPUAttrLength); }
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// Sub-Arch name.
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StringRef getSubArch() const { return StringRef(SubArchCStr, SubArchLength); }
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};
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ArchNames<ARM::ArchKind> ARCHNames[] = {
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#define ARM_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, ARCH_BASE_EXT) \
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{NAME, sizeof(NAME) - 1, CPU_ATTR, sizeof(CPU_ATTR) - 1, SUB_ARCH, \
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sizeof(SUB_ARCH) - 1, ARCH_FPU, ARCH_BASE_EXT, ARM::ArchKind::ID, ARCH_ATTR},
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#include "llvm/Support/ARMTargetParser.def"
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};
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ArchNames<AArch64::ArchKind> AArch64ARCHNames[] = {
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#define AARCH64_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, ARCH_BASE_EXT) \
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{NAME, sizeof(NAME) - 1, CPU_ATTR, sizeof(CPU_ATTR) - 1, SUB_ARCH, \
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sizeof(SUB_ARCH) - 1, ARCH_FPU, ARCH_BASE_EXT, AArch64::ArchKind::ID, ARCH_ATTR},
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#include "llvm/Support/AArch64TargetParser.def"
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};
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// List of Arch Extension names.
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// FIXME: TableGen this.
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static const struct {
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const char *NameCStr;
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size_t NameLength;
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unsigned ID;
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const char *Feature;
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const char *NegFeature;
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StringRef getName() const { return StringRef(NameCStr, NameLength); }
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} ARCHExtNames[] = {
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#define ARM_ARCH_EXT_NAME(NAME, ID, FEATURE, NEGFEATURE) \
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{ NAME, sizeof(NAME) - 1, ID, FEATURE, NEGFEATURE },
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#include "llvm/Support/ARMTargetParser.def"
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},AArch64ARCHExtNames[] = {
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#define AARCH64_ARCH_EXT_NAME(NAME, ID, FEATURE, NEGFEATURE) \
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{ NAME, sizeof(NAME) - 1, ID, FEATURE, NEGFEATURE },
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#include "llvm/Support/AArch64TargetParser.def"
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};
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// List of HWDiv names (use getHWDivSynonym) and which architectural
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// features they correspond to (use getHWDivFeatures).
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// FIXME: TableGen this.
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static const struct {
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const char *NameCStr;
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size_t NameLength;
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unsigned ID;
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StringRef getName() const { return StringRef(NameCStr, NameLength); }
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} HWDivNames[] = {
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#define ARM_HW_DIV_NAME(NAME, ID) { NAME, sizeof(NAME) - 1, ID },
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#include "llvm/Support/ARMTargetParser.def"
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};
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// List of CPU names and their arches.
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// The same CPU can have multiple arches and can be default on multiple arches.
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// When finding the Arch for a CPU, first-found prevails. Sort them accordingly.
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// When this becomes table-generated, we'd probably need two tables.
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// FIXME: TableGen this.
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template <typename T> struct CpuNames {
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const char *NameCStr;
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size_t NameLength;
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T ArchID;
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bool Default; // is $Name the default CPU for $ArchID ?
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unsigned DefaultExtensions;
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StringRef getName() const { return StringRef(NameCStr, NameLength); }
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};
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CpuNames<ARM::ArchKind> CPUNames[] = {
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#define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \
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{ NAME, sizeof(NAME) - 1, ARM::ArchKind::ID, IS_DEFAULT, DEFAULT_EXT },
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#include "llvm/Support/ARMTargetParser.def"
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};
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CpuNames<AArch64::ArchKind> AArch64CPUNames[] = {
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#define AARCH64_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \
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{ NAME, sizeof(NAME) - 1, AArch64::ArchKind::ID, IS_DEFAULT, DEFAULT_EXT },
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#include "llvm/Support/AArch64TargetParser.def"
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};
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} // namespace
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// ======================================================= //
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// Information by ID
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// ======================================================= //
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StringRef ARM::getFPUName(unsigned FPUKind) {
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if (FPUKind >= ARM::FK_LAST)
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return StringRef();
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return FPUNames[FPUKind].getName();
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}
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FPUVersion ARM::getFPUVersion(unsigned FPUKind) {
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if (FPUKind >= ARM::FK_LAST)
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return FPUVersion::NONE;
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return FPUNames[FPUKind].FPUVersion;
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}
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ARM::NeonSupportLevel ARM::getFPUNeonSupportLevel(unsigned FPUKind) {
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if (FPUKind >= ARM::FK_LAST)
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return ARM::NeonSupportLevel::None;
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return FPUNames[FPUKind].NeonSupport;
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}
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ARM::FPURestriction ARM::getFPURestriction(unsigned FPUKind) {
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if (FPUKind >= ARM::FK_LAST)
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return ARM::FPURestriction::None;
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return FPUNames[FPUKind].Restriction;
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}
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unsigned llvm::ARM::getDefaultFPU(StringRef CPU, ArchKind AK) {
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if (CPU == "generic")
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return ARCHNames[static_cast<unsigned>(AK)].DefaultFPU;
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return StringSwitch<unsigned>(CPU)
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#define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \
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.Case(NAME, DEFAULT_FPU)
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#include "llvm/Support/ARMTargetParser.def"
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.Default(ARM::FK_INVALID);
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}
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unsigned llvm::ARM::getDefaultExtensions(StringRef CPU, ArchKind AK) {
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if (CPU == "generic")
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return ARCHNames[static_cast<unsigned>(AK)].ArchBaseExtensions;
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return StringSwitch<unsigned>(CPU)
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#define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \
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.Case(NAME, ARCHNames[static_cast<unsigned>(ARM::ArchKind::ID)]\
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.ArchBaseExtensions | DEFAULT_EXT)
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#include "llvm/Support/ARMTargetParser.def"
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.Default(ARM::AEK_INVALID);
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}
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bool llvm::ARM::getHWDivFeatures(unsigned HWDivKind,
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std::vector<StringRef> &Features) {
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if (HWDivKind == ARM::AEK_INVALID)
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return false;
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if (HWDivKind & ARM::AEK_HWDIVARM)
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Features.push_back("+hwdiv-arm");
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else
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Features.push_back("-hwdiv-arm");
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if (HWDivKind & ARM::AEK_HWDIVTHUMB)
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Features.push_back("+hwdiv");
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else
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Features.push_back("-hwdiv");
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return true;
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}
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bool llvm::ARM::getExtensionFeatures(unsigned Extensions,
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std::vector<StringRef> &Features) {
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if (Extensions == ARM::AEK_INVALID)
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return false;
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if (Extensions & ARM::AEK_CRC)
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Features.push_back("+crc");
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else
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Features.push_back("-crc");
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if (Extensions & ARM::AEK_DSP)
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Features.push_back("+dsp");
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else
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Features.push_back("-dsp");
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if (Extensions & ARM::AEK_RAS)
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Features.push_back("+ras");
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else
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Features.push_back("-ras");
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if (Extensions & ARM::AEK_DOTPROD)
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Features.push_back("+dotprod");
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else
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Features.push_back("-dotprod");
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return getHWDivFeatures(Extensions, Features);
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}
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bool llvm::ARM::getFPUFeatures(unsigned FPUKind,
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std::vector<StringRef> &Features) {
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if (FPUKind >= ARM::FK_LAST || FPUKind == ARM::FK_INVALID)
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return false;
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// fp-only-sp and d16 subtarget features are independent of each other, so we
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// must enable/disable both.
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switch (FPUNames[FPUKind].Restriction) {
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case ARM::FPURestriction::SP_D16:
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Features.push_back("+fp-only-sp");
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Features.push_back("+d16");
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break;
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case ARM::FPURestriction::D16:
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Features.push_back("-fp-only-sp");
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Features.push_back("+d16");
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break;
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case ARM::FPURestriction::None:
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Features.push_back("-fp-only-sp");
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Features.push_back("-d16");
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break;
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}
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// FPU version subtarget features are inclusive of lower-numbered ones, so
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// enable the one corresponding to this version and disable all that are
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// higher. We also have to make sure to disable fp16 when vfp4 is disabled,
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// as +vfp4 implies +fp16 but -vfp4 does not imply -fp16.
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switch (FPUNames[FPUKind].FPUVersion) {
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case ARM::FPUVersion::VFPV5:
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Features.push_back("+fp-armv8");
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break;
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case ARM::FPUVersion::VFPV4:
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Features.push_back("+vfp4");
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Features.push_back("-fp-armv8");
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break;
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case ARM::FPUVersion::VFPV3_FP16:
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Features.push_back("+vfp3");
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Features.push_back("+fp16");
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Features.push_back("-vfp4");
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Features.push_back("-fp-armv8");
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break;
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case ARM::FPUVersion::VFPV3:
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Features.push_back("+vfp3");
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Features.push_back("-fp16");
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Features.push_back("-vfp4");
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Features.push_back("-fp-armv8");
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break;
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case ARM::FPUVersion::VFPV2:
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Features.push_back("+vfp2");
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Features.push_back("-vfp3");
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Features.push_back("-fp16");
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Features.push_back("-vfp4");
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Features.push_back("-fp-armv8");
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break;
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case ARM::FPUVersion::NONE:
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Features.push_back("-vfp2");
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Features.push_back("-vfp3");
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Features.push_back("-fp16");
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Features.push_back("-vfp4");
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Features.push_back("-fp-armv8");
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break;
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}
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// crypto includes neon, so we handle this similarly to FPU version.
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switch (FPUNames[FPUKind].NeonSupport) {
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case ARM::NeonSupportLevel::Crypto:
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Features.push_back("+neon");
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Features.push_back("+crypto");
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break;
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case ARM::NeonSupportLevel::Neon:
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Features.push_back("+neon");
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Features.push_back("-crypto");
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break;
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case ARM::NeonSupportLevel::None:
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Features.push_back("-neon");
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Features.push_back("-crypto");
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break;
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}
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return true;
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}
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StringRef llvm::ARM::getArchName(ArchKind AK) {
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return ARCHNames[static_cast<unsigned>(AK)].getName();
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}
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StringRef llvm::ARM::getCPUAttr(ArchKind AK) {
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return ARCHNames[static_cast<unsigned>(AK)].getCPUAttr();
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}
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StringRef llvm::ARM::getSubArch(ArchKind AK) {
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return ARCHNames[static_cast<unsigned>(AK)].getSubArch();
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}
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unsigned llvm::ARM::getArchAttr(ArchKind AK) {
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return ARCHNames[static_cast<unsigned>(AK)].ArchAttr;
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}
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StringRef llvm::ARM::getArchExtName(unsigned ArchExtKind) {
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for (const auto AE : ARCHExtNames) {
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if (ArchExtKind == AE.ID)
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return AE.getName();
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}
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return StringRef();
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}
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StringRef llvm::ARM::getArchExtFeature(StringRef ArchExt) {
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if (ArchExt.startswith("no")) {
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StringRef ArchExtBase(ArchExt.substr(2));
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for (const auto AE : ARCHExtNames) {
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if (AE.NegFeature && ArchExtBase == AE.getName())
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return StringRef(AE.NegFeature);
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}
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}
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for (const auto AE : ARCHExtNames) {
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if (AE.Feature && ArchExt == AE.getName())
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return StringRef(AE.Feature);
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}
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return StringRef();
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}
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StringRef llvm::ARM::getHWDivName(unsigned HWDivKind) {
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for (const auto D : HWDivNames) {
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if (HWDivKind == D.ID)
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return D.getName();
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}
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return StringRef();
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}
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StringRef llvm::ARM::getDefaultCPU(StringRef Arch) {
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ArchKind AK = parseArch(Arch);
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if (AK == ARM::ArchKind::INVALID)
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return StringRef();
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// Look for multiple AKs to find the default for pair AK+Name.
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for (const auto CPU : CPUNames) {
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if (CPU.ArchID == AK && CPU.Default)
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return CPU.getName();
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}
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// If we can't find a default then target the architecture instead
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return "generic";
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}
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StringRef llvm::AArch64::getFPUName(unsigned FPUKind) {
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return ARM::getFPUName(FPUKind);
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}
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ARM::FPUVersion AArch64::getFPUVersion(unsigned FPUKind) {
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return ARM::getFPUVersion(FPUKind);
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}
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ARM::NeonSupportLevel AArch64::getFPUNeonSupportLevel(unsigned FPUKind) {
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return ARM::getFPUNeonSupportLevel( FPUKind);
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}
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ARM::FPURestriction AArch64::getFPURestriction(unsigned FPUKind) {
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return ARM::getFPURestriction(FPUKind);
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}
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unsigned llvm::AArch64::getDefaultFPU(StringRef CPU, ArchKind AK) {
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if (CPU == "generic")
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return AArch64ARCHNames[static_cast<unsigned>(AK)].DefaultFPU;
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return StringSwitch<unsigned>(CPU)
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#define AARCH64_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \
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.Case(NAME, DEFAULT_FPU)
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#include "llvm/Support/AArch64TargetParser.def"
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.Default(ARM::FK_INVALID);
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}
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unsigned llvm::AArch64::getDefaultExtensions(StringRef CPU, ArchKind AK) {
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if (CPU == "generic")
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return AArch64ARCHNames[static_cast<unsigned>(AK)].ArchBaseExtensions;
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return StringSwitch<unsigned>(CPU)
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#define AARCH64_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \
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.Case(NAME, \
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AArch64ARCHNames[static_cast<unsigned>(AArch64::ArchKind::ID)] \
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.ArchBaseExtensions | \
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DEFAULT_EXT)
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#include "llvm/Support/AArch64TargetParser.def"
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.Default(AArch64::AEK_INVALID);
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}
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bool llvm::AArch64::getExtensionFeatures(unsigned Extensions,
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std::vector<StringRef> &Features) {
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|
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if (Extensions == AArch64::AEK_INVALID)
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return false;
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if (Extensions & AArch64::AEK_FP)
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Features.push_back("+fp-armv8");
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if (Extensions & AArch64::AEK_SIMD)
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Features.push_back("+neon");
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if (Extensions & AArch64::AEK_CRC)
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Features.push_back("+crc");
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if (Extensions & AArch64::AEK_CRYPTO)
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Features.push_back("+crypto");
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if (Extensions & AArch64::AEK_DOTPROD)
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Features.push_back("+dotprod");
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if (Extensions & AArch64::AEK_FP16)
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Features.push_back("+fullfp16");
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if (Extensions & AArch64::AEK_PROFILE)
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Features.push_back("+spe");
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if (Extensions & AArch64::AEK_RAS)
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Features.push_back("+ras");
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if (Extensions & AArch64::AEK_LSE)
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Features.push_back("+lse");
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if (Extensions & AArch64::AEK_RDM)
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Features.push_back("+rdm");
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if (Extensions & AArch64::AEK_SVE)
|
|
Features.push_back("+sve");
|
|
if (Extensions & AArch64::AEK_RCPC)
|
|
Features.push_back("+rcpc");
|
|
|
|
return true;
|
|
}
|
|
|
|
bool llvm::AArch64::getFPUFeatures(unsigned FPUKind,
|
|
std::vector<StringRef> &Features) {
|
|
return ARM::getFPUFeatures(FPUKind, Features);
|
|
}
|
|
|
|
bool llvm::AArch64::getArchFeatures(AArch64::ArchKind AK,
|
|
std::vector<StringRef> &Features) {
|
|
if (AK == AArch64::ArchKind::ARMV8_1A)
|
|
Features.push_back("+v8.1a");
|
|
if (AK == AArch64::ArchKind::ARMV8_2A)
|
|
Features.push_back("+v8.2a");
|
|
if (AK == AArch64::ArchKind::ARMV8_3A)
|
|
Features.push_back("+v8.3a");
|
|
if (AK == AArch64::ArchKind::ARMV8_4A)
|
|
Features.push_back("+v8.4a");
|
|
|
|
return AK != AArch64::ArchKind::INVALID;
|
|
}
|
|
|
|
StringRef llvm::AArch64::getArchName(ArchKind AK) {
|
|
return AArch64ARCHNames[static_cast<unsigned>(AK)].getName();
|
|
}
|
|
|
|
StringRef llvm::AArch64::getCPUAttr(ArchKind AK) {
|
|
return AArch64ARCHNames[static_cast<unsigned>(AK)].getCPUAttr();
|
|
}
|
|
|
|
StringRef llvm::AArch64::getSubArch(ArchKind AK) {
|
|
return AArch64ARCHNames[static_cast<unsigned>(AK)].getSubArch();
|
|
}
|
|
|
|
unsigned llvm::AArch64::getArchAttr(ArchKind AK) {
|
|
return AArch64ARCHNames[static_cast<unsigned>(AK)].ArchAttr;
|
|
}
|
|
|
|
StringRef llvm::AArch64::getArchExtName(unsigned ArchExtKind) {
|
|
for (const auto &AE : AArch64ARCHExtNames)
|
|
if (ArchExtKind == AE.ID)
|
|
return AE.getName();
|
|
return StringRef();
|
|
}
|
|
|
|
StringRef llvm::AArch64::getArchExtFeature(StringRef ArchExt) {
|
|
if (ArchExt.startswith("no")) {
|
|
StringRef ArchExtBase(ArchExt.substr(2));
|
|
for (const auto &AE : AArch64ARCHExtNames) {
|
|
if (AE.NegFeature && ArchExtBase == AE.getName())
|
|
return StringRef(AE.NegFeature);
|
|
}
|
|
}
|
|
|
|
for (const auto &AE : AArch64ARCHExtNames)
|
|
if (AE.Feature && ArchExt == AE.getName())
|
|
return StringRef(AE.Feature);
|
|
return StringRef();
|
|
}
|
|
|
|
StringRef llvm::AArch64::getDefaultCPU(StringRef Arch) {
|
|
AArch64::ArchKind AK = parseArch(Arch);
|
|
if (AK == ArchKind::INVALID)
|
|
return StringRef();
|
|
|
|
// Look for multiple AKs to find the default for pair AK+Name.
|
|
for (const auto &CPU : AArch64CPUNames)
|
|
if (CPU.ArchID == AK && CPU.Default)
|
|
return CPU.getName();
|
|
|
|
// If we can't find a default then target the architecture instead
|
|
return "generic";
|
|
}
|
|
|
|
unsigned llvm::AArch64::checkArchVersion(StringRef Arch) {
|
|
if (Arch.size() >= 2 && Arch[0] == 'v' && std::isdigit(Arch[1]))
|
|
return (Arch[1] - 48);
|
|
return 0;
|
|
}
|
|
|
|
// ======================================================= //
|
|
// Parsers
|
|
// ======================================================= //
|
|
|
|
static StringRef getHWDivSynonym(StringRef HWDiv) {
|
|
return StringSwitch<StringRef>(HWDiv)
|
|
.Case("thumb,arm", "arm,thumb")
|
|
.Default(HWDiv);
|
|
}
|
|
|
|
static StringRef getFPUSynonym(StringRef FPU) {
|
|
return StringSwitch<StringRef>(FPU)
|
|
.Cases("fpa", "fpe2", "fpe3", "maverick", "invalid") // Unsupported
|
|
.Case("vfp2", "vfpv2")
|
|
.Case("vfp3", "vfpv3")
|
|
.Case("vfp4", "vfpv4")
|
|
.Case("vfp3-d16", "vfpv3-d16")
|
|
.Case("vfp4-d16", "vfpv4-d16")
|
|
.Cases("fp4-sp-d16", "vfpv4-sp-d16", "fpv4-sp-d16")
|
|
.Cases("fp4-dp-d16", "fpv4-dp-d16", "vfpv4-d16")
|
|
.Case("fp5-sp-d16", "fpv5-sp-d16")
|
|
.Cases("fp5-dp-d16", "fpv5-dp-d16", "fpv5-d16")
|
|
// FIXME: Clang uses it, but it's bogus, since neon defaults to vfpv3.
|
|
.Case("neon-vfpv3", "neon")
|
|
.Default(FPU);
|
|
}
|
|
|
|
static StringRef getArchSynonym(StringRef Arch) {
|
|
return StringSwitch<StringRef>(Arch)
|
|
.Case("v5", "v5t")
|
|
.Case("v5e", "v5te")
|
|
.Case("v6j", "v6")
|
|
.Case("v6hl", "v6k")
|
|
.Cases("v6m", "v6sm", "v6s-m", "v6-m")
|
|
.Cases("v6z", "v6zk", "v6kz")
|
|
.Cases("v7", "v7a", "v7hl", "v7l", "v7-a")
|
|
.Case("v7r", "v7-r")
|
|
.Case("v7m", "v7-m")
|
|
.Case("v7em", "v7e-m")
|
|
.Cases("v8", "v8a", "v8l", "aarch64", "arm64", "v8-a")
|
|
.Case("v8.1a", "v8.1-a")
|
|
.Case("v8.2a", "v8.2-a")
|
|
.Case("v8.3a", "v8.3-a")
|
|
.Case("v8.4a", "v8.4-a")
|
|
.Case("v8r", "v8-r")
|
|
.Case("v8m.base", "v8-m.base")
|
|
.Case("v8m.main", "v8-m.main")
|
|
.Default(Arch);
|
|
}
|
|
|
|
// MArch is expected to be of the form (arm|thumb)?(eb)?(v.+)?(eb)?, but
|
|
// (iwmmxt|xscale)(eb)? is also permitted. If the former, return
|
|
// "v.+", if the latter, return unmodified string, minus 'eb'.
|
|
// If invalid, return empty string.
|
|
StringRef llvm::ARM::getCanonicalArchName(StringRef Arch) {
|
|
size_t offset = StringRef::npos;
|
|
StringRef A = Arch;
|
|
StringRef Error = "";
|
|
|
|
// Begins with "arm" / "thumb", move past it.
|
|
if (A.startswith("arm64"))
|
|
offset = 5;
|
|
else if (A.startswith("arm"))
|
|
offset = 3;
|
|
else if (A.startswith("thumb"))
|
|
offset = 5;
|
|
else if (A.startswith("aarch64")) {
|
|
offset = 7;
|
|
// AArch64 uses "_be", not "eb" suffix.
|
|
if (A.find("eb") != StringRef::npos)
|
|
return Error;
|
|
if (A.substr(offset, 3) == "_be")
|
|
offset += 3;
|
|
}
|
|
|
|
// Ex. "armebv7", move past the "eb".
|
|
if (offset != StringRef::npos && A.substr(offset, 2) == "eb")
|
|
offset += 2;
|
|
// Or, if it ends with eb ("armv7eb"), chop it off.
|
|
else if (A.endswith("eb"))
|
|
A = A.substr(0, A.size() - 2);
|
|
// Trim the head
|
|
if (offset != StringRef::npos)
|
|
A = A.substr(offset);
|
|
|
|
// Empty string means offset reached the end, which means it's valid.
|
|
if (A.empty())
|
|
return Arch;
|
|
|
|
// Only match non-marketing names
|
|
if (offset != StringRef::npos) {
|
|
// Must start with 'vN'.
|
|
if (A.size() >= 2 && (A[0] != 'v' || !std::isdigit(A[1])))
|
|
return Error;
|
|
// Can't have an extra 'eb'.
|
|
if (A.find("eb") != StringRef::npos)
|
|
return Error;
|
|
}
|
|
|
|
// Arch will either be a 'v' name (v7a) or a marketing name (xscale).
|
|
return A;
|
|
}
|
|
|
|
unsigned llvm::ARM::parseHWDiv(StringRef HWDiv) {
|
|
StringRef Syn = getHWDivSynonym(HWDiv);
|
|
for (const auto D : HWDivNames) {
|
|
if (Syn == D.getName())
|
|
return D.ID;
|
|
}
|
|
return ARM::AEK_INVALID;
|
|
}
|
|
|
|
unsigned llvm::ARM::parseFPU(StringRef FPU) {
|
|
StringRef Syn = getFPUSynonym(FPU);
|
|
for (const auto F : FPUNames) {
|
|
if (Syn == F.getName())
|
|
return F.ID;
|
|
}
|
|
return ARM::FK_INVALID;
|
|
}
|
|
|
|
// Allows partial match, ex. "v7a" matches "armv7a".
|
|
ARM::ArchKind ARM::parseArch(StringRef Arch) {
|
|
Arch = getCanonicalArchName(Arch);
|
|
StringRef Syn = getArchSynonym(Arch);
|
|
for (const auto A : ARCHNames) {
|
|
if (A.getName().endswith(Syn))
|
|
return A.ID;
|
|
}
|
|
return ARM::ArchKind::INVALID;
|
|
}
|
|
|
|
unsigned llvm::ARM::parseArchExt(StringRef ArchExt) {
|
|
for (const auto A : ARCHExtNames) {
|
|
if (ArchExt == A.getName())
|
|
return A.ID;
|
|
}
|
|
return ARM::AEK_INVALID;
|
|
}
|
|
|
|
ARM::ArchKind llvm::ARM::parseCPUArch(StringRef CPU) {
|
|
for (const auto C : CPUNames) {
|
|
if (CPU == C.getName())
|
|
return C.ArchID;
|
|
}
|
|
return ARM::ArchKind::INVALID;
|
|
}
|
|
|
|
void llvm::ARM::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values) {
|
|
for (const CpuNames<ARM::ArchKind> &Arch : CPUNames) {
|
|
if (Arch.ArchID != ARM::ArchKind::INVALID)
|
|
Values.push_back(Arch.getName());
|
|
}
|
|
}
|
|
|
|
void llvm::AArch64::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values) {
|
|
for (const CpuNames<AArch64::ArchKind> &Arch : AArch64CPUNames) {
|
|
if (Arch.ArchID != AArch64::ArchKind::INVALID)
|
|
Values.push_back(Arch.getName());
|
|
}
|
|
}
|
|
|
|
// ARM, Thumb, AArch64
|
|
ARM::ISAKind ARM::parseArchISA(StringRef Arch) {
|
|
return StringSwitch<ARM::ISAKind>(Arch)
|
|
.StartsWith("aarch64", ARM::ISAKind::AARCH64)
|
|
.StartsWith("arm64", ARM::ISAKind::AARCH64)
|
|
.StartsWith("thumb", ARM::ISAKind::THUMB)
|
|
.StartsWith("arm", ARM::ISAKind::ARM)
|
|
.Default(ARM::ISAKind::INVALID);
|
|
}
|
|
|
|
// Little/Big endian
|
|
ARM::EndianKind ARM::parseArchEndian(StringRef Arch) {
|
|
if (Arch.startswith("armeb") || Arch.startswith("thumbeb") ||
|
|
Arch.startswith("aarch64_be"))
|
|
return ARM::EndianKind::BIG;
|
|
|
|
if (Arch.startswith("arm") || Arch.startswith("thumb")) {
|
|
if (Arch.endswith("eb"))
|
|
return ARM::EndianKind::BIG;
|
|
else
|
|
return ARM::EndianKind::LITTLE;
|
|
}
|
|
|
|
if (Arch.startswith("aarch64"))
|
|
return ARM::EndianKind::LITTLE;
|
|
|
|
return ARM::EndianKind::INVALID;
|
|
}
|
|
|
|
// Profile A/R/M
|
|
ARM::ProfileKind ARM::parseArchProfile(StringRef Arch) {
|
|
Arch = getCanonicalArchName(Arch);
|
|
switch (parseArch(Arch)) {
|
|
case ARM::ArchKind::ARMV6M:
|
|
case ARM::ArchKind::ARMV7M:
|
|
case ARM::ArchKind::ARMV7EM:
|
|
case ARM::ArchKind::ARMV8MMainline:
|
|
case ARM::ArchKind::ARMV8MBaseline:
|
|
return ARM::ProfileKind::M;
|
|
case ARM::ArchKind::ARMV7R:
|
|
case ARM::ArchKind::ARMV8R:
|
|
return ARM::ProfileKind::R;
|
|
case ARM::ArchKind::ARMV7A:
|
|
case ARM::ArchKind::ARMV7VE:
|
|
case ARM::ArchKind::ARMV7K:
|
|
case ARM::ArchKind::ARMV8A:
|
|
case ARM::ArchKind::ARMV8_1A:
|
|
case ARM::ArchKind::ARMV8_2A:
|
|
case ARM::ArchKind::ARMV8_3A:
|
|
case ARM::ArchKind::ARMV8_4A:
|
|
return ARM::ProfileKind::A;
|
|
case ARM::ArchKind::ARMV2:
|
|
case ARM::ArchKind::ARMV2A:
|
|
case ARM::ArchKind::ARMV3:
|
|
case ARM::ArchKind::ARMV3M:
|
|
case ARM::ArchKind::ARMV4:
|
|
case ARM::ArchKind::ARMV4T:
|
|
case ARM::ArchKind::ARMV5T:
|
|
case ARM::ArchKind::ARMV5TE:
|
|
case ARM::ArchKind::ARMV5TEJ:
|
|
case ARM::ArchKind::ARMV6:
|
|
case ARM::ArchKind::ARMV6K:
|
|
case ARM::ArchKind::ARMV6T2:
|
|
case ARM::ArchKind::ARMV6KZ:
|
|
case ARM::ArchKind::ARMV7S:
|
|
case ARM::ArchKind::IWMMXT:
|
|
case ARM::ArchKind::IWMMXT2:
|
|
case ARM::ArchKind::XSCALE:
|
|
case ARM::ArchKind::INVALID:
|
|
return ARM::ProfileKind::INVALID;
|
|
}
|
|
llvm_unreachable("Unhandled architecture");
|
|
}
|
|
|
|
// Version number (ex. v7 = 7).
|
|
unsigned llvm::ARM::parseArchVersion(StringRef Arch) {
|
|
Arch = getCanonicalArchName(Arch);
|
|
switch (parseArch(Arch)) {
|
|
case ARM::ArchKind::ARMV2:
|
|
case ARM::ArchKind::ARMV2A:
|
|
return 2;
|
|
case ARM::ArchKind::ARMV3:
|
|
case ARM::ArchKind::ARMV3M:
|
|
return 3;
|
|
case ARM::ArchKind::ARMV4:
|
|
case ARM::ArchKind::ARMV4T:
|
|
return 4;
|
|
case ARM::ArchKind::ARMV5T:
|
|
case ARM::ArchKind::ARMV5TE:
|
|
case ARM::ArchKind::IWMMXT:
|
|
case ARM::ArchKind::IWMMXT2:
|
|
case ARM::ArchKind::XSCALE:
|
|
case ARM::ArchKind::ARMV5TEJ:
|
|
return 5;
|
|
case ARM::ArchKind::ARMV6:
|
|
case ARM::ArchKind::ARMV6K:
|
|
case ARM::ArchKind::ARMV6T2:
|
|
case ARM::ArchKind::ARMV6KZ:
|
|
case ARM::ArchKind::ARMV6M:
|
|
return 6;
|
|
case ARM::ArchKind::ARMV7A:
|
|
case ARM::ArchKind::ARMV7VE:
|
|
case ARM::ArchKind::ARMV7R:
|
|
case ARM::ArchKind::ARMV7M:
|
|
case ARM::ArchKind::ARMV7S:
|
|
case ARM::ArchKind::ARMV7EM:
|
|
case ARM::ArchKind::ARMV7K:
|
|
return 7;
|
|
case ARM::ArchKind::ARMV8A:
|
|
case ARM::ArchKind::ARMV8_1A:
|
|
case ARM::ArchKind::ARMV8_2A:
|
|
case ARM::ArchKind::ARMV8_3A:
|
|
case ARM::ArchKind::ARMV8_4A:
|
|
case ARM::ArchKind::ARMV8R:
|
|
case ARM::ArchKind::ARMV8MBaseline:
|
|
case ARM::ArchKind::ARMV8MMainline:
|
|
return 8;
|
|
case ARM::ArchKind::INVALID:
|
|
return 0;
|
|
}
|
|
llvm_unreachable("Unhandled architecture");
|
|
}
|
|
|
|
StringRef llvm::ARM::computeDefaultTargetABI(const Triple &TT, StringRef CPU) {
|
|
StringRef ArchName =
|
|
CPU.empty() ? TT.getArchName() : ARM::getArchName(ARM::parseCPUArch(CPU));
|
|
|
|
if (TT.isOSBinFormatMachO()) {
|
|
if (TT.getEnvironment() == Triple::EABI ||
|
|
TT.getOS() == Triple::UnknownOS ||
|
|
llvm::ARM::parseArchProfile(ArchName) == ARM::ProfileKind::M)
|
|
return "aapcs";
|
|
if (TT.isWatchABI())
|
|
return "aapcs16";
|
|
return "apcs-gnu";
|
|
} else if (TT.isOSWindows())
|
|
// FIXME: this is invalid for WindowsCE.
|
|
return "aapcs";
|
|
|
|
// Select the default based on the platform.
|
|
switch (TT.getEnvironment()) {
|
|
case Triple::Android:
|
|
case Triple::GNUEABI:
|
|
case Triple::GNUEABIHF:
|
|
case Triple::MuslEABI:
|
|
case Triple::MuslEABIHF:
|
|
return "aapcs-linux";
|
|
case Triple::EABIHF:
|
|
case Triple::EABI:
|
|
return "aapcs";
|
|
default:
|
|
if (TT.isOSNetBSD())
|
|
return "apcs-gnu";
|
|
if (TT.isOSOpenBSD())
|
|
return "aapcs-linux";
|
|
return "aapcs";
|
|
}
|
|
}
|
|
|
|
StringRef llvm::AArch64::getCanonicalArchName(StringRef Arch) {
|
|
return ARM::getCanonicalArchName(Arch);
|
|
}
|
|
|
|
unsigned llvm::AArch64::parseFPU(StringRef FPU) {
|
|
return ARM::parseFPU(FPU);
|
|
}
|
|
|
|
// Allows partial match, ex. "v8a" matches "armv8a".
|
|
AArch64::ArchKind AArch64::parseArch(StringRef Arch) {
|
|
Arch = getCanonicalArchName(Arch);
|
|
if (checkArchVersion(Arch) < 8)
|
|
return ArchKind::INVALID;
|
|
|
|
StringRef Syn = getArchSynonym(Arch);
|
|
for (const auto A : AArch64ARCHNames) {
|
|
if (A.getName().endswith(Syn))
|
|
return A.ID;
|
|
}
|
|
return ArchKind::INVALID;
|
|
}
|
|
|
|
AArch64::ArchExtKind llvm::AArch64::parseArchExt(StringRef ArchExt) {
|
|
for (const auto A : AArch64ARCHExtNames) {
|
|
if (ArchExt == A.getName())
|
|
return static_cast<ArchExtKind>(A.ID);
|
|
}
|
|
return AArch64::AEK_INVALID;
|
|
}
|
|
|
|
AArch64::ArchKind llvm::AArch64::parseCPUArch(StringRef CPU) {
|
|
for (const auto C : AArch64CPUNames) {
|
|
if (CPU == C.getName())
|
|
return C.ArchID;
|
|
}
|
|
return ArchKind::INVALID;
|
|
}
|
|
|
|
// ARM, Thumb, AArch64
|
|
ARM::ISAKind AArch64::parseArchISA(StringRef Arch) {
|
|
return ARM::parseArchISA(Arch);
|
|
}
|
|
|
|
// Little/Big endian
|
|
ARM::EndianKind AArch64::parseArchEndian(StringRef Arch) {
|
|
return ARM::parseArchEndian(Arch);
|
|
}
|
|
|
|
// Profile A/R/M
|
|
ARM::ProfileKind AArch64::parseArchProfile(StringRef Arch) {
|
|
return ARM::parseArchProfile(Arch);
|
|
}
|
|
|
|
// Version number (ex. v8 = 8).
|
|
unsigned llvm::AArch64::parseArchVersion(StringRef Arch) {
|
|
return ARM::parseArchVersion(Arch);
|
|
}
|
|
|
|
bool llvm::AArch64::isX18ReservedByDefault(const Triple &TT) {
|
|
return TT.isOSDarwin() || TT.isOSFuchsia() || TT.isOSWindows();
|
|
}
|