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e196d2ab43
Summary: Adds a new kind of MachineOperand: MO_Placeholder. This operand must not appear in the MIR and only exists as a way of creating an 'uninitialized' operand until a matcher function overwrites it. Depends on D30046, D29712 Reviewers: t.p.northover, ab, rovka, aditya_nandakumar, javed.absar, qcolombet Reviewed By: qcolombet Subscribers: dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D30089 llvm-svn: 297782
112 lines
5.7 KiB
TableGen
112 lines
5.7 KiB
TableGen
// RUN: llvm-tblgen -gen-global-isel -I %p/../../include %s | FileCheck %s
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include "llvm/Target/Target.td"
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//===- Define the necessary boilerplate for our test target. --------------===//
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def MyTargetISA : InstrInfo;
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def MyTarget : Target { let InstructionSet = MyTargetISA; }
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def R0 : Register<"r0"> { let Namespace = "MyTarget"; }
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def GPR32 : RegisterClass<"MyTarget", [i32], 32, (add R0)>;
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class I<dag OOps, dag IOps, list<dag> Pat>
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: Instruction {
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let Namespace = "MyTarget";
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let OutOperandList = OOps;
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let InOperandList = IOps;
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let Pattern = Pat;
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}
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//===- Test the function definition boilerplate. --------------------------===//
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// CHECK: bool MyTargetInstructionSelector::selectImpl(MachineInstr &I) const {
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// CHECK: MachineFunction &MF = *I.getParent()->getParent();
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// CHECK: const MachineRegisterInfo &MRI = MF.getRegInfo();
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//===- Test a simple pattern with regclass operands. ----------------------===//
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// CHECK-LABEL: if ((I.getOpcode() == TargetOpcode::G_ADD) &&
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// CHECK-NEXT: ((/* dst */ (MRI.getType(I.getOperand(0).getReg()) == (LLT::scalar(32))) &&
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// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(I.getOperand(0).getReg(), MRI, TRI))))) &&
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// CHECK-NEXT: ((/* src1 */ (MRI.getType(I.getOperand(1).getReg()) == (LLT::scalar(32))) &&
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// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(I.getOperand(1).getReg(), MRI, TRI))))) &&
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// CHECK-NEXT: ((/* src2 */ (MRI.getType(I.getOperand(2).getReg()) == (LLT::scalar(32))) &&
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// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(I.getOperand(2).getReg(), MRI, TRI)))))) {
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// CHECK-NEXT: // (add:i32 GPR32:i32:$src1, GPR32:i32:$src2) => (ADD:i32 GPR32:i32:$src1, GPR32:i32:$src2)
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// CHECK-NEXT: I.setDesc(TII.get(MyTarget::ADD));
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// CHECK-NEXT: MachineInstr &NewI = I;
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// CHECK: constrainSelectedInstRegOperands(NewI, TII, TRI, RBI);
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// CHECK-NEXT: return true;
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// CHECK-NEXT: }
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def ADD : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2),
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[(set GPR32:$dst, (add GPR32:$src1, GPR32:$src2))]>;
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// CHECK-LABEL: if ((I.getOpcode() == TargetOpcode::G_MUL) &&
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// CHECK-NEXT: ((/* dst */ (MRI.getType(I.getOperand(0).getReg()) == (LLT::scalar(32))) &&
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// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(I.getOperand(0).getReg(), MRI, TRI))))) &&
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// CHECK-NEXT: ((/* src1 */ (MRI.getType(I.getOperand(1).getReg()) == (LLT::scalar(32))) &&
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// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(I.getOperand(1).getReg(), MRI, TRI))))) &&
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// CHECK-NEXT: ((/* src2 */ (MRI.getType(I.getOperand(2).getReg()) == (LLT::scalar(32))) &&
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// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(I.getOperand(2).getReg(), MRI, TRI)))))) {
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// CHECK-NEXT: // (mul:i32 GPR32:i32:$src1, GPR32:i32:$src2) => (MUL:i32 GPR32:i32:$src2, GPR32:i32:$src1)
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// CHECK-NEXT: MachineInstrBuilder MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(MyTarget::MUL));
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// CHECK-NEXT: MIB.add(I.getOperand(0)/*dst*/);
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// CHECK-NEXT: MIB.add(I.getOperand(2)/*src2*/);
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// CHECK-NEXT: MIB.add(I.getOperand(1)/*src1*/);
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// CHECK-NEXT: MIB.setMemRefs(I.memoperands_begin(), I.memoperands_end());
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// CHECK-NEXT: I.eraseFromParent();
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// CHECK-NEXT: MachineInstr &NewI = *MIB;
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// CHECK: constrainSelectedInstRegOperands(NewI, TII, TRI, RBI);
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// CHECK-NEXT: return true;
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// CHECK-NEXT: }
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def MUL : I<(outs GPR32:$dst), (ins GPR32:$src2, GPR32:$src1),
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[(set GPR32:$dst, (mul GPR32:$src1, GPR32:$src2))]>;
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//===- Test a simple pattern with constant immediate operands. ------------===//
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//
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// This must precede the 3-register variants because constant immediates have
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// priority over register banks.
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// CHECK-LABEL: if ((I.getOpcode() == TargetOpcode::G_XOR) &&
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// CHECK-NEXT: ((/* dst */ (MRI.getType(I.getOperand(0).getReg()) == (LLT::scalar(32))) &&
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// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(I.getOperand(0).getReg(), MRI, TRI))))) &&
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// CHECK-NEXT: ((/* Wm */ (MRI.getType(I.getOperand(1).getReg()) == (LLT::scalar(32))) &&
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// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(I.getOperand(1).getReg(), MRI, TRI))))) &&
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// CHECK-NEXT: ((/* Operand 2 */ (MRI.getType(I.getOperand(2).getReg()) == (LLT::scalar(32))) &&
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// CHECK-NEXT: (isOperandImmEqual(I.getOperand(2), -1, MRI))))) {
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// CHECK-NEXT: // (xor:i32 GPR32:i32:$Wm, -1:i32) => (ORN:i32 R0:i32, GPR32:i32:$Wm)
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// CHECK-NEXT: MachineInstrBuilder MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(MyTarget::ORN));
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// CHECK-NEXT: MIB.add(I.getOperand(0)/*dst*/);
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// CHECK-NEXT: MIB.addReg(MyTarget::R0);
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// CHECK-NEXT: MIB.add(I.getOperand(1)/*Wm*/);
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// CHECK-NEXT: MIB.setMemRefs(I.memoperands_begin(), I.memoperands_end());
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// CHECK-NEXT: I.eraseFromParent();
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// CHECK-NEXT: MachineInstr &NewI = *MIB;
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// CHECK: constrainSelectedInstRegOperands(NewI, TII, TRI, RBI);
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// CHECK-NEXT: return true;
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// CHECK-NEXT: }
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def ORN : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), []>;
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def : Pat<(not GPR32:$Wm), (ORN R0, GPR32:$Wm)>;
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//===- Test a pattern with an MBB operand. --------------------------------===//
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// CHECK-LABEL: if ((I.getOpcode() == TargetOpcode::G_BR) &&
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// CHECK-NEXT: ((/* target */ (I.getOperand(0).isMBB())))) {
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// CHECK-NEXT: // (br (bb:Other):$target) => (BR (bb:Other):$target)
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// CHECK-NEXT: I.setDesc(TII.get(MyTarget::BR));
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// CHECK-NEXT: MachineInstr &NewI = I;
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// CHECK: constrainSelectedInstRegOperands(NewI, TII, TRI, RBI);
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// CHECK-NEXT: return true;
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// CHECK-NEXT: }
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def BR : I<(outs), (ins unknown:$target),
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[(br bb:$target)]>;
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