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235 lines
8.4 KiB
C++
235 lines
8.4 KiB
C++
//===-- XCoreISelDAGToDAG.cpp - A dag to dag inst selector for XCore ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the XCore target.
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//
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//===----------------------------------------------------------------------===//
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#include "XCore.h"
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#include "XCoreISelLowering.h"
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#include "XCoreTargetMachine.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/Function.h"
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#include "llvm/Intrinsics.h"
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#include "llvm/CallingConv.h"
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#include "llvm/Constants.h"
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#include "llvm/LLVMContext.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include <queue>
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#include <set>
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using namespace llvm;
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/// XCoreDAGToDAGISel - XCore specific code to select XCore machine
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/// instructions for SelectionDAG operations.
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///
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namespace {
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class XCoreDAGToDAGISel : public SelectionDAGISel {
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XCoreTargetLowering &Lowering;
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const XCoreSubtarget &Subtarget;
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public:
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XCoreDAGToDAGISel(XCoreTargetMachine &TM)
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: SelectionDAGISel(TM),
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Lowering(*TM.getTargetLowering()),
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Subtarget(*TM.getSubtargetImpl()) { }
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SDNode *Select(SDValue Op);
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/// getI32Imm - Return a target constant with the specified value, of type
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/// i32.
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inline SDValue getI32Imm(unsigned Imm) {
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return CurDAG->getTargetConstant(Imm, MVT::i32);
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}
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// Complex Pattern Selectors.
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bool SelectADDRspii(SDValue Op, SDValue Addr, SDValue &Base,
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SDValue &Offset);
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bool SelectADDRdpii(SDValue Op, SDValue Addr, SDValue &Base,
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SDValue &Offset);
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bool SelectADDRcpii(SDValue Op, SDValue Addr, SDValue &Base,
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SDValue &Offset);
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virtual void InstructionSelect();
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virtual const char *getPassName() const {
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return "XCore DAG->DAG Pattern Instruction Selection";
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}
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// Include the pieces autogenerated from the target description.
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#include "XCoreGenDAGISel.inc"
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};
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} // end anonymous namespace
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/// createXCoreISelDag - This pass converts a legalized DAG into a
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/// XCore-specific DAG, ready for instruction scheduling.
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///
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FunctionPass *llvm::createXCoreISelDag(XCoreTargetMachine &TM) {
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return new XCoreDAGToDAGISel(TM);
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}
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bool XCoreDAGToDAGISel::SelectADDRspii(SDValue Op, SDValue Addr,
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SDValue &Base, SDValue &Offset) {
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FrameIndexSDNode *FIN = 0;
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if ((FIN = dyn_cast<FrameIndexSDNode>(Addr))) {
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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return true;
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}
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if (Addr.getOpcode() == ISD::ADD) {
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ConstantSDNode *CN = 0;
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if ((FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
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&& (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
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&& (CN->getSExtValue() % 4 == 0 && CN->getSExtValue() >= 0)) {
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// Constant positive word offset from frame index
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
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Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32);
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return true;
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}
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}
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return false;
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}
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bool XCoreDAGToDAGISel::SelectADDRdpii(SDValue Op, SDValue Addr,
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SDValue &Base, SDValue &Offset) {
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if (Addr.getOpcode() == XCoreISD::DPRelativeWrapper) {
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Base = Addr.getOperand(0);
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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return true;
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}
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if (Addr.getOpcode() == ISD::ADD) {
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ConstantSDNode *CN = 0;
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if ((Addr.getOperand(0).getOpcode() == XCoreISD::DPRelativeWrapper)
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&& (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
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&& (CN->getSExtValue() % 4 == 0)) {
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// Constant word offset from a object in the data region
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Base = Addr.getOperand(0).getOperand(0);
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Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32);
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return true;
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}
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}
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return false;
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}
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bool XCoreDAGToDAGISel::SelectADDRcpii(SDValue Op, SDValue Addr,
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SDValue &Base, SDValue &Offset) {
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if (Addr.getOpcode() == XCoreISD::CPRelativeWrapper) {
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Base = Addr.getOperand(0);
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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return true;
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}
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if (Addr.getOpcode() == ISD::ADD) {
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ConstantSDNode *CN = 0;
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if ((Addr.getOperand(0).getOpcode() == XCoreISD::CPRelativeWrapper)
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&& (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
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&& (CN->getSExtValue() % 4 == 0)) {
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// Constant word offset from a object in the data region
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Base = Addr.getOperand(0).getOperand(0);
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Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32);
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return true;
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}
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}
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return false;
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}
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/// InstructionSelect - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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void XCoreDAGToDAGISel::
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InstructionSelect() {
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DEBUG(BB->dump());
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// Select target instructions for the DAG.
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SelectRoot(*CurDAG);
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CurDAG->RemoveDeadNodes();
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}
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SDNode *XCoreDAGToDAGISel::Select(SDValue Op) {
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SDNode *N = Op.getNode();
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DebugLoc dl = N->getDebugLoc();
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EVT NVT = N->getValueType(0);
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if (NVT == MVT::i32) {
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switch (N->getOpcode()) {
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default: break;
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case ISD::Constant: {
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if (Predicate_immMskBitp(N)) {
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SDValue MskSize = Transform_msksize_xform(N);
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return CurDAG->getTargetNode(XCore::MKMSK_rus, dl, MVT::i32, MskSize);
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}
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else if (! Predicate_immU16(N)) {
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unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
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SDValue CPIdx =
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CurDAG->getTargetConstantPool(ConstantInt::get(
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Type::getInt32Ty(*CurDAG->getContext()), Val),
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TLI.getPointerTy());
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return CurDAG->getTargetNode(XCore::LDWCP_lru6, dl, MVT::i32,
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MVT::Other, CPIdx,
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CurDAG->getEntryNode());
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}
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break;
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}
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case ISD::SMUL_LOHI: {
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// FIXME fold addition into the macc instruction
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if (!Subtarget.isXS1A()) {
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SDValue Zero(CurDAG->getTargetNode(XCore::LDC_ru6, dl, MVT::i32,
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CurDAG->getTargetConstant(0, MVT::i32)), 0);
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SDValue Ops[] = { Zero, Zero, Op.getOperand(0), Op.getOperand(1) };
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SDNode *ResNode = CurDAG->getTargetNode(XCore::MACCS_l4r, dl,
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MVT::i32, MVT::i32, Ops, 4);
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ReplaceUses(SDValue(N, 0), SDValue(ResNode, 1));
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ReplaceUses(SDValue(N, 1), SDValue(ResNode, 0));
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return NULL;
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}
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break;
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}
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case ISD::UMUL_LOHI: {
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// FIXME fold addition into the macc / lmul instruction
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SDValue Zero(CurDAG->getTargetNode(XCore::LDC_ru6, dl, MVT::i32,
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CurDAG->getTargetConstant(0, MVT::i32)), 0);
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SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
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Zero, Zero };
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SDNode *ResNode = CurDAG->getTargetNode(XCore::LMUL_l6r, dl, MVT::i32,
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MVT::i32, Ops, 4);
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ReplaceUses(SDValue(N, 0), SDValue(ResNode, 1));
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ReplaceUses(SDValue(N, 1), SDValue(ResNode, 0));
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return NULL;
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}
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case XCoreISD::LADD: {
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if (!Subtarget.isXS1A()) {
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SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
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Op.getOperand(2) };
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return CurDAG->getTargetNode(XCore::LADD_l5r, dl, MVT::i32, MVT::i32,
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Ops, 3);
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}
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break;
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}
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case XCoreISD::LSUB: {
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if (!Subtarget.isXS1A()) {
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SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
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Op.getOperand(2) };
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return CurDAG->getTargetNode(XCore::LSUB_l5r, dl, MVT::i32, MVT::i32,
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Ops, 3);
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}
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break;
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}
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// Other cases are autogenerated.
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}
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}
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return SelectCode(Op);
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}
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