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b555d38aa1
This allows for a much more efficient encoding for small negative numbers by storing the sign bit first and negating the rest of the bits. This was already being used for OPC_CheckInteger. For every in tree target this affects, the table got smaller. R600GenDAGISel.inc saw the largest reduction of 7K. I did have to add a new opcode for StringIntegers used for register class ids and subregister indices since we don't have the integer value to encode. The enum name is emitted directly into the table. Previously assumed the enum would expand to a positive 7-bit number. We might be able to just shift that right by 1 and assume it is a positive 6 bit number, but that will need more investigation.
40 lines
1.3 KiB
TableGen
40 lines
1.3 KiB
TableGen
// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include %s | FileCheck %s
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include "llvm/Target/Target.td"
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def TestTargetInstrInfo : InstrInfo;
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def TestTarget : Target {
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let InstructionSet = TestTargetInstrInfo;
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}
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let Namespace = "TestNamespace" in {
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def R0 : Register<"r0">;
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foreach i = 0...127 in {
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def GPR#i : RegisterClass<"TestTarget", [i32], 32,
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(add R0)>;
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}
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def GPRAbove127 : RegisterClass<"TestTarget", [i32], 32,
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(add R0)>;
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} // end Namespace TestNamespace
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// CHECK: OPC_CheckOpcode, TARGET_VAL(ISD::ADD),
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// CHECK-NEXT: OPC_RecordChild0, // #0 = $src
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// CHECK-NEXT: OPC_Scope, 14, /*->20*/ // 2 children in Scope
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// CHECK-NEXT: OPC_CheckChild1Integer, 0,
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// CHECK-NEXT: OPC_EmitInteger, MVT::i32, 0|128,2/*256*/,
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// CHECK-NEXT: OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
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// CHECK-NEXT: MVT::i32, 2/*#Ops*/, 1, 0,
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def : Pat<(i32 (add i32:$src, (i32 0))),
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(COPY_TO_REGCLASS GPRAbove127, GPR0:$src)>;
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// CHECK: OPC_CheckChild1Integer, 2,
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// CHECK-NEXT: OPC_EmitStringInteger, MVT::i32, TestNamespace::GPR127RegClassID,
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// CHECK-NEXT: OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
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// CHECK-NEXT: MVT::i32, 2/*#Ops*/, 1, 0,
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def : Pat<(i32 (add i32:$src, (i32 1))),
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(COPY_TO_REGCLASS GPR127, GPR0:$src)>;
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