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https://github.com/RPCS3/llvm-mirror.git
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07e93d8663
Summary:
Implement BUFFER_ATOMIC_CMPSWAP{,_X2} instructions on all GCN targets, and FLAT_ATOMIC_CMPSWAP{,_X2} on CI+.
32-bit instruction variants tested manually on Kabini and Bonaire. Tests and parts of code provided by Jan Veselý.
Patch by: Vedran Miletić
Reviewers: arsenm, tstellarAMD, nhaehnle
Subscribers: jvesely, scchan, kanarayan, arsenm
Differential Revision: http://reviews.llvm.org/D17280
llvm-svn: 265170
261 lines
9.1 KiB
TableGen
261 lines
9.1 KiB
TableGen
//===-- AMDGPUInstrInfo.td - AMDGPU DAG nodes --------------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains DAG node defintions for the AMDGPU target.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// AMDGPU DAG Profiles
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//===----------------------------------------------------------------------===//
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def AMDGPUDTIntTernaryOp : SDTypeProfile<1, 3, [
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SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3>
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]>;
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def AMDGPUTrigPreOp : SDTypeProfile<1, 2,
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[SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]
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>;
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def AMDGPULdExpOp : SDTypeProfile<1, 2,
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[SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]
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>;
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def AMDGPUFPClassOp : SDTypeProfile<1, 2,
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[SDTCisInt<0>, SDTCisFP<1>, SDTCisInt<2>]
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>;
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def AMDGPUDivScaleOp : SDTypeProfile<2, 3,
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[SDTCisFP<0>, SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisSameAs<0, 4>]
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>;
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// float, float, float, vcc
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def AMDGPUFmasOp : SDTypeProfile<1, 4,
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[SDTCisFP<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisInt<4>]
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>;
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//===----------------------------------------------------------------------===//
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// AMDGPU DAG Nodes
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//
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// This argument to this node is a dword address.
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def AMDGPUdwordaddr : SDNode<"AMDGPUISD::DWORDADDR", SDTIntUnaryOp>;
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def AMDGPUcos : SDNode<"AMDGPUISD::COS_HW", SDTFPUnaryOp>;
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def AMDGPUsin : SDNode<"AMDGPUISD::SIN_HW", SDTFPUnaryOp>;
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// out = a - floor(a)
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def AMDGPUfract : SDNode<"AMDGPUISD::FRACT", SDTFPUnaryOp>;
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// out = 1.0 / a
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def AMDGPUrcp : SDNode<"AMDGPUISD::RCP", SDTFPUnaryOp>;
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// out = 1.0 / sqrt(a)
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def AMDGPUrsq : SDNode<"AMDGPUISD::RSQ", SDTFPUnaryOp>;
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// out = 1.0 / sqrt(a)
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def AMDGPUrsq_legacy : SDNode<"AMDGPUISD::RSQ_LEGACY", SDTFPUnaryOp>;
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// out = 1.0 / sqrt(a) result clamped to +/- max_float.
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def AMDGPUrsq_clamp : SDNode<"AMDGPUISD::RSQ_CLAMP", SDTFPUnaryOp>;
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def AMDGPUldexp : SDNode<"AMDGPUISD::LDEXP", AMDGPULdExpOp>;
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def AMDGPUfp_class : SDNode<"AMDGPUISD::FP_CLASS", AMDGPUFPClassOp>;
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// out = max(a, b) a and b are floats, where a nan comparison fails.
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// This is not commutative because this gives the second operand:
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// x < nan ? x : nan -> nan
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// nan < x ? nan : x -> x
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def AMDGPUfmax_legacy : SDNode<"AMDGPUISD::FMAX_LEGACY", SDTFPBinOp,
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[]
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>;
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def AMDGPUclamp : SDNode<"AMDGPUISD::CLAMP", SDTFPTernaryOp, []>;
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// out = max(a, b) a and b are signed ints
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def AMDGPUsmax : SDNode<"AMDGPUISD::SMAX", SDTIntBinOp,
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[SDNPCommutative, SDNPAssociative]
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>;
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// out = max(a, b) a and b are unsigned ints
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def AMDGPUumax : SDNode<"AMDGPUISD::UMAX", SDTIntBinOp,
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[SDNPCommutative, SDNPAssociative]
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>;
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// out = min(a, b) a and b are floats, where a nan comparison fails.
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def AMDGPUfmin_legacy : SDNode<"AMDGPUISD::FMIN_LEGACY", SDTFPBinOp,
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[]
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>;
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// FIXME: TableGen doesn't like commutative instructions with more
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// than 2 operands.
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// out = max(a, b, c) a, b and c are floats
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def AMDGPUfmax3 : SDNode<"AMDGPUISD::FMAX3", SDTFPTernaryOp,
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[/*SDNPCommutative, SDNPAssociative*/]
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>;
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// out = max(a, b, c) a, b, and c are signed ints
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def AMDGPUsmax3 : SDNode<"AMDGPUISD::SMAX3", AMDGPUDTIntTernaryOp,
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[/*SDNPCommutative, SDNPAssociative*/]
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>;
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// out = max(a, b, c) a, b and c are unsigned ints
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def AMDGPUumax3 : SDNode<"AMDGPUISD::UMAX3", AMDGPUDTIntTernaryOp,
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[/*SDNPCommutative, SDNPAssociative*/]
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>;
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// out = min(a, b, c) a, b and c are floats
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def AMDGPUfmin3 : SDNode<"AMDGPUISD::FMIN3", SDTFPTernaryOp,
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[/*SDNPCommutative, SDNPAssociative*/]
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>;
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// out = min(a, b, c) a, b and c are signed ints
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def AMDGPUsmin3 : SDNode<"AMDGPUISD::SMIN3", AMDGPUDTIntTernaryOp,
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[/*SDNPCommutative, SDNPAssociative*/]
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>;
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// out = min(a, b) a and b are unsigned ints
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def AMDGPUumin3 : SDNode<"AMDGPUISD::UMIN3", AMDGPUDTIntTernaryOp,
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[/*SDNPCommutative, SDNPAssociative*/]
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>;
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// out = (src0 + src1 > 0xFFFFFFFF) ? 1 : 0
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def AMDGPUcarry : SDNode<"AMDGPUISD::CARRY", SDTIntBinOp, []>;
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// out = (src1 > src0) ? 1 : 0
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def AMDGPUborrow : SDNode<"AMDGPUISD::BORROW", SDTIntBinOp, []>;
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def AMDGPUcvt_f32_ubyte0 : SDNode<"AMDGPUISD::CVT_F32_UBYTE0",
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SDTIntToFPOp, []>;
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def AMDGPUcvt_f32_ubyte1 : SDNode<"AMDGPUISD::CVT_F32_UBYTE1",
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SDTIntToFPOp, []>;
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def AMDGPUcvt_f32_ubyte2 : SDNode<"AMDGPUISD::CVT_F32_UBYTE2",
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SDTIntToFPOp, []>;
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def AMDGPUcvt_f32_ubyte3 : SDNode<"AMDGPUISD::CVT_F32_UBYTE3",
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SDTIntToFPOp, []>;
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// urecip - This operation is a helper for integer division, it returns the
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// result of 1 / a as a fractional unsigned integer.
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// out = (2^32 / a) + e
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// e is rounding error
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def AMDGPUurecip : SDNode<"AMDGPUISD::URECIP", SDTIntUnaryOp>;
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// Special case divide preop and flags.
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def AMDGPUdiv_scale : SDNode<"AMDGPUISD::DIV_SCALE", AMDGPUDivScaleOp>;
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// Special case divide FMA with scale and flags (src0 = Quotient,
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// src1 = Denominator, src2 = Numerator).
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def AMDGPUdiv_fmas : SDNode<"AMDGPUISD::DIV_FMAS", AMDGPUFmasOp>;
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// Single or double precision division fixup.
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// Special case divide fixup and flags(src0 = Quotient, src1 =
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// Denominator, src2 = Numerator).
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def AMDGPUdiv_fixup : SDNode<"AMDGPUISD::DIV_FIXUP", SDTFPTernaryOp>;
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// Look Up 2.0 / pi src0 with segment select src1[4:0]
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def AMDGPUtrig_preop : SDNode<"AMDGPUISD::TRIG_PREOP", AMDGPUTrigPreOp>;
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def AMDGPUregister_load : SDNode<"AMDGPUISD::REGISTER_LOAD",
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SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
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[SDNPHasChain, SDNPMayLoad]>;
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def AMDGPUregister_store : SDNode<"AMDGPUISD::REGISTER_STORE",
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SDTypeProfile<0, 3, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
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[SDNPHasChain, SDNPMayStore]>;
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// MSKOR instructions are atomic memory instructions used mainly for storing
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// 8-bit and 16-bit values. The definition is:
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//
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// MSKOR(dst, mask, src) MEM[dst] = ((MEM[dst] & ~mask) | src)
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//
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// src0: vec4(src, 0, 0, mask)
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// src1: dst - rat offset (aka pointer) in dwords
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def AMDGPUstore_mskor : SDNode<"AMDGPUISD::STORE_MSKOR",
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SDTypeProfile<0, 2, []>,
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[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
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def AMDGPUatomic_cmp_swap : SDNode<"AMDGPUISD::ATOMIC_CMP_SWAP",
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SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisVec<2>]>,
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[SDNPHasChain, SDNPMayStore, SDNPMayLoad,
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SDNPMemOperand]>;
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def AMDGPUround : SDNode<"ISD::FROUND",
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SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>>;
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def AMDGPUbfe_u32 : SDNode<"AMDGPUISD::BFE_U32", AMDGPUDTIntTernaryOp>;
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def AMDGPUbfe_i32 : SDNode<"AMDGPUISD::BFE_I32", AMDGPUDTIntTernaryOp>;
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def AMDGPUbfi : SDNode<"AMDGPUISD::BFI", AMDGPUDTIntTernaryOp>;
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def AMDGPUbfm : SDNode<"AMDGPUISD::BFM", SDTIntBinOp>;
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def AMDGPUffbh_u32 : SDNode<"AMDGPUISD::FFBH_U32", SDTIntUnaryOp>;
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// Signed and unsigned 24-bit mulitply. The highest 8-bits are ignore when
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// performing the mulitply. The result is a 32-bit value.
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def AMDGPUmul_u24 : SDNode<"AMDGPUISD::MUL_U24", SDTIntBinOp,
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[SDNPCommutative]
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>;
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def AMDGPUmul_i24 : SDNode<"AMDGPUISD::MUL_I24", SDTIntBinOp,
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[SDNPCommutative]
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>;
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def AMDGPUmad_u24 : SDNode<"AMDGPUISD::MAD_U24", AMDGPUDTIntTernaryOp,
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[]
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>;
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def AMDGPUmad_i24 : SDNode<"AMDGPUISD::MAD_I24", AMDGPUDTIntTernaryOp,
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[]
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>;
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def AMDGPUsmed3 : SDNode<"AMDGPUISD::SMED3", AMDGPUDTIntTernaryOp,
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[]
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>;
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def AMDGPUumed3 : SDNode<"AMDGPUISD::UMED3", AMDGPUDTIntTernaryOp,
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[]
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>;
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def AMDGPUfmed3 : SDNode<"AMDGPUISD::FMED3", SDTFPTernaryOp, []>;
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def AMDGPUsendmsg : SDNode<"AMDGPUISD::SENDMSG",
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SDTypeProfile<0, 1, [SDTCisInt<0>]>,
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[SDNPHasChain, SDNPInGlue]>;
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def AMDGPUinterp_mov : SDNode<"AMDGPUISD::INTERP_MOV",
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SDTypeProfile<1, 3, [SDTCisFP<0>]>,
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[SDNPInGlue]>;
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def AMDGPUinterp_p1 : SDNode<"AMDGPUISD::INTERP_P1",
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SDTypeProfile<1, 3, [SDTCisFP<0>]>,
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[SDNPInGlue, SDNPOutGlue]>;
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def AMDGPUinterp_p2 : SDNode<"AMDGPUISD::INTERP_P2",
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SDTypeProfile<1, 4, [SDTCisFP<0>]>,
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[SDNPInGlue]>;
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//===----------------------------------------------------------------------===//
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// Flow Control Profile Types
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//===----------------------------------------------------------------------===//
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// Branch instruction where second and third are basic blocks
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def SDTIL_BRCond : SDTypeProfile<0, 2, [
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SDTCisVT<0, OtherVT>
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]>;
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//===----------------------------------------------------------------------===//
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// Flow Control DAG Nodes
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//===----------------------------------------------------------------------===//
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def IL_brcond : SDNode<"AMDGPUISD::BRANCH_COND", SDTIL_BRCond, [SDNPHasChain]>;
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//===----------------------------------------------------------------------===//
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// Call/Return DAG Nodes
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//===----------------------------------------------------------------------===//
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def IL_retflag : SDNode<"AMDGPUISD::RET_FLAG", SDTNone,
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[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
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