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aaf2db6c80
cmpxchg[8|16]b uses RBX as one of its argument. In other words, using this instruction clobbers RBX as it is defined to hold one the input. When the backend uses dynamically allocated stack, RBX is used as a reserved register for the base pointer. Reserved registers have special semantic that only the target understands and enforces, because of that, the register allocator don’t use them, but also, don’t try to make sure they are used properly (remember it does not know how they are supposed to be used). Therefore, when RBX is used as a reserved register but defined by something that is not compatible with that use, the register allocator will not fix the surrounding code to make sure it gets saved and restored properly around the broken code. This is the responsibility of the target to do the right thing with its reserved register. To fix that, when the base pointer needs to be preserved, we use a different pseudo instruction for cmpxchg that save rbx. That pseudo takes two more arguments than the regular instruction: - One is the value to be copied into RBX to set the proper value for the comparison. - The other is the virtual register holding the save of the value of RBX as the base pointer. This saving is done as part of isel (i.e., we emit a copy from rbx). cmpxchg_save_rbx <regular cmpxchg args>, input_for_rbx_reg, save_of_rbx_as_bp This gets expanded into: rbx = copy input_for_rbx_reg cmpxchg <regular cmpxchg args> rbx = save_of_rbx_as_bp Note: The actual modeling of the pseudo is a bit more complicated to make sure the interferes that appears after the pseudo gets expanded are properly modeled before that expansion. This fixes PR26883. llvm-svn: 263325
294 lines
8.1 KiB
LLVM
294 lines
8.1 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-macosx10.9 -verify-machineinstrs -mattr=cx16 | FileCheck %s
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@var = global i128 0
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define i128 @val_compare_and_swap(i128* %p, i128 %oldval, i128 %newval) {
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; CHECK-LABEL: val_compare_and_swap:
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; Due to the scheduling right after isel for cmpxchg and given the
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; machine scheduler and copy coalescer do not mess up with physical
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; register live-ranges, we end up with a useless copy.
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;
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; CHECK: movq %rcx, [[TMP:%r[0-9a-z]+]]
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; CHECK: movq %rsi, %rax
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; CHECK: movq %r8, %rcx
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; CHECK: movq [[TMP]], %rbx
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; CHECK: lock
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; CHECK: cmpxchg16b (%rdi)
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%pair = cmpxchg i128* %p, i128 %oldval, i128 %newval acquire acquire
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%val = extractvalue { i128, i1 } %pair, 0
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ret i128 %val
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}
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define void @fetch_and_nand(i128* %p, i128 %bits) {
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; CHECK-LABEL: fetch_and_nand:
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; CHECK-DAG: movq %rdx, [[INCHI:%[a-z0-9]+]]
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; CHECK-DAG: movq (%rdi), %rax
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; CHECK-DAG: movq 8(%rdi), %rdx
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; CHECK: [[LOOP:.?LBB[0-9]+_[0-9]+]]:
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; CHECK: movq %rdx, %rcx
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; CHECK: andq [[INCHI]], %rcx
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; CHECK: movq %rax, %rbx
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; INCLO equivalent comes in in %rsi, so it makes sense it stays there.
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; CHECK: andq %rsi, %rbx
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; CHECK: notq %rbx
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; CHECK: notq %rcx
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; CHECK: lock
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; CHECK: cmpxchg16b (%rdi)
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; CHECK: jne [[LOOP]]
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; CHECK: movq %rax, _var
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; CHECK: movq %rdx, _var+8
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%val = atomicrmw nand i128* %p, i128 %bits release
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store i128 %val, i128* @var, align 16
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ret void
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}
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define void @fetch_and_or(i128* %p, i128 %bits) {
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; CHECK-LABEL: fetch_and_or:
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; CHECK-DAG: movq %rdx, [[INCHI:%[a-z0-9]+]]
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; CHECK-DAG: movq (%rdi), %rax
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; CHECK-DAG: movq 8(%rdi), %rdx
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; CHECK: [[LOOP:.?LBB[0-9]+_[0-9]+]]:
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; CHECK: movq %rax, %rbx
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; INCLO equivalent comes in in %rsi, so it makes sense it stays there.
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; CHECK: orq %rsi, %rbx
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; CHECK: movq %rdx, %rcx
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; CHECK: orq [[INCHI]], %rcx
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; CHECK: lock
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; CHECK: cmpxchg16b (%rdi)
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; CHECK: jne [[LOOP]]
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; CHECK: movq %rax, _var
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; CHECK: movq %rdx, _var+8
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%val = atomicrmw or i128* %p, i128 %bits seq_cst
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store i128 %val, i128* @var, align 16
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ret void
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}
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define void @fetch_and_add(i128* %p, i128 %bits) {
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; CHECK-LABEL: fetch_and_add:
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; CHECK-DAG: movq %rdx, [[INCHI:%[a-z0-9]+]]
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; CHECK-DAG: movq (%rdi), %rax
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; CHECK-DAG: movq 8(%rdi), %rdx
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; CHECK: [[LOOP:.?LBB[0-9]+_[0-9]+]]:
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; CHECK: movq %rax, %rbx
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; INCLO equivalent comes in in %rsi, so it makes sense it stays there.
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; CHECK: addq %rsi, %rbx
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; CHECK: movq %rdx, %rcx
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; CHECK: adcq [[INCHI]], %rcx
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; CHECK: lock
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; CHECK: cmpxchg16b (%rdi)
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; CHECK: jne [[LOOP]]
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; CHECK: movq %rax, _var
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; CHECK: movq %rdx, _var+8
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%val = atomicrmw add i128* %p, i128 %bits seq_cst
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store i128 %val, i128* @var, align 16
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ret void
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}
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define void @fetch_and_sub(i128* %p, i128 %bits) {
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; CHECK-LABEL: fetch_and_sub:
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; CHECK-DAG: movq %rdx, [[INCHI:%[a-z0-9]+]]
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; CHECK-DAG: movq (%rdi), %rax
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; CHECK-DAG: movq 8(%rdi), %rdx
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; CHECK: [[LOOP:.?LBB[0-9]+_[0-9]+]]:
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; CHECK: movq %rax, %rbx
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; INCLO equivalent comes in in %rsi, so it makes sense it stays there.
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; CHECK: subq %rsi, %rbx
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; CHECK: movq %rdx, %rcx
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; CHECK: sbbq [[INCHI]], %rcx
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; CHECK: lock
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; CHECK: cmpxchg16b (%rdi)
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; CHECK: jne [[LOOP]]
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; CHECK: movq %rax, _var
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; CHECK: movq %rdx, _var+8
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%val = atomicrmw sub i128* %p, i128 %bits seq_cst
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store i128 %val, i128* @var, align 16
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ret void
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}
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define void @fetch_and_min(i128* %p, i128 %bits) {
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; CHECK-LABEL: fetch_and_min:
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; CHECK-DAG: movq %rdx, [[INCHI:%[a-z0-9]+]]
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; CHECK-DAG: movq (%rdi), %rax
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; CHECK-DAG: movq 8(%rdi), %rdx
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; CHECK: [[LOOP:.?LBB[0-9]+_[0-9]+]]:
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; CHECK: cmpq
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; CHECK: sbbq
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; CHECK: setg
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; CHECK: cmovneq %rax, %rbx
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; CHECK: movq [[INCHI]], %rcx
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; CHECK: cmovneq %rdx, %rcx
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; CHECK: lock
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; CHECK: cmpxchg16b (%rdi)
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; CHECK: jne [[LOOP]]
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; CHECK: movq %rax, _var
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; CHECK: movq %rdx, _var+8
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%val = atomicrmw min i128* %p, i128 %bits seq_cst
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store i128 %val, i128* @var, align 16
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ret void
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}
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define void @fetch_and_max(i128* %p, i128 %bits) {
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; CHECK-LABEL: fetch_and_max:
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; CHECK-DAG: movq %rdx, [[INCHI:%[a-z0-9]+]]
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; CHECK-DAG: movq (%rdi), %rax
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; CHECK-DAG: movq 8(%rdi), %rdx
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; CHECK: [[LOOP:.?LBB[0-9]+_[0-9]+]]:
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; CHECK: cmpq
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; CHECK: sbbq
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; CHECK: setge
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; CHECK: cmovneq %rax, %rbx
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; CHECK: movq [[INCHI]], %rcx
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; CHECK: cmovneq %rdx, %rcx
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; CHECK: lock
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; CHECK: cmpxchg16b (%rdi)
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; CHECK: jne [[LOOP]]
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; CHECK: movq %rax, _var
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; CHECK: movq %rdx, _var+8
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%val = atomicrmw max i128* %p, i128 %bits seq_cst
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store i128 %val, i128* @var, align 16
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ret void
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}
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define void @fetch_and_umin(i128* %p, i128 %bits) {
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; CHECK-LABEL: fetch_and_umin:
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; CHECK-DAG: movq %rdx, [[INCHI:%[a-z0-9]+]]
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; CHECK-DAG: movq (%rdi), %rax
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; CHECK-DAG: movq 8(%rdi), %rdx
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; CHECK: [[LOOP:.?LBB[0-9]+_[0-9]+]]:
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; CHECK: cmpq
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; CHECK: sbbq
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; CHECK: seta
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; CHECK: cmovneq %rax, %rbx
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; CHECK: movq [[INCHI]], %rcx
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; CHECK: cmovneq %rdx, %rcx
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; CHECK: lock
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; CHECK: cmpxchg16b (%rdi)
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; CHECK: jne [[LOOP]]
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; CHECK: movq %rax, _var
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; CHECK: movq %rdx, _var+8
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%val = atomicrmw umin i128* %p, i128 %bits seq_cst
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store i128 %val, i128* @var, align 16
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ret void
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}
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define void @fetch_and_umax(i128* %p, i128 %bits) {
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; CHECK-LABEL: fetch_and_umax:
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; CHECK-DAG: movq %rdx, [[INCHI:%[a-z0-9]+]]
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; CHECK-DAG: movq (%rdi), %rax
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; CHECK-DAG: movq 8(%rdi), %rdx
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; CHECK: [[LOOP:.?LBB[0-9]+_[0-9]+]]:
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; CHECK: cmpq
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; CHECK: sbbq
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; CHECK: setb
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; CHECK: cmovneq %rax, %rbx
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; CHECK: movq [[INCHI]], %rcx
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; CHECK: cmovneq %rdx, %rcx
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; CHECK: lock
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; CHECK: cmpxchg16b (%rdi)
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; CHECK: jne [[LOOP]]
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; CHECK: movq %rax, _var
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; CHECK: movq %rdx, _var+8
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%val = atomicrmw umax i128* %p, i128 %bits seq_cst
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store i128 %val, i128* @var, align 16
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ret void
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}
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define i128 @atomic_load_seq_cst(i128* %p) {
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; CHECK-LABEL: atomic_load_seq_cst:
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; CHECK: xorl %eax, %eax
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; CHECK: xorl %edx, %edx
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; CHECK: xorl %ecx, %ecx
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; CHECK: xorl %ebx, %ebx
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; CHECK: lock
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; CHECK: cmpxchg16b (%rdi)
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%r = load atomic i128, i128* %p seq_cst, align 16
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ret i128 %r
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}
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define i128 @atomic_load_relaxed(i128* %p) {
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; CHECK: atomic_load_relaxed:
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; CHECK: xorl %eax, %eax
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; CHECK: xorl %edx, %edx
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; CHECK: xorl %ecx, %ecx
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; CHECK: xorl %ebx, %ebx
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; CHECK: lock
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; CHECK: cmpxchg16b (%rdi)
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%r = load atomic i128, i128* %p monotonic, align 16
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ret i128 %r
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}
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define void @atomic_store_seq_cst(i128* %p, i128 %in) {
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; CHECK-LABEL: atomic_store_seq_cst:
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; CHECK: movq %rdx, %rcx
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; CHECK: movq %rsi, %rbx
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; CHECK: movq (%rdi), %rax
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; CHECK: movq 8(%rdi), %rdx
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; CHECK: [[LOOP:.?LBB[0-9]+_[0-9]+]]:
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; CHECK: lock
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; CHECK: cmpxchg16b (%rdi)
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; CHECK: jne [[LOOP]]
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; CHECK-NOT: callq ___sync_lock_test_and_set_16
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store atomic i128 %in, i128* %p seq_cst, align 16
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ret void
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}
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define void @atomic_store_release(i128* %p, i128 %in) {
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; CHECK-LABEL: atomic_store_release:
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; CHECK: movq %rdx, %rcx
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; CHECK: movq %rsi, %rbx
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; CHECK: movq (%rdi), %rax
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; CHECK: movq 8(%rdi), %rdx
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; CHECK: [[LOOP:.?LBB[0-9]+_[0-9]+]]:
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; CHECK: lock
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; CHECK: cmpxchg16b (%rdi)
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; CHECK: jne [[LOOP]]
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store atomic i128 %in, i128* %p release, align 16
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ret void
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}
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define void @atomic_store_relaxed(i128* %p, i128 %in) {
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; CHECK-LABEL: atomic_store_relaxed:
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; CHECK: movq %rdx, %rcx
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; CHECK: movq %rsi, %rbx
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; CHECK: movq (%rdi), %rax
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; CHECK: movq 8(%rdi), %rdx
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; CHECK: [[LOOP:.?LBB[0-9]+_[0-9]+]]:
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; CHECK: lock
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; CHECK: cmpxchg16b (%rdi)
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; CHECK: jne [[LOOP]]
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store atomic i128 %in, i128* %p unordered, align 16
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ret void
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}
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