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130 lines
6.7 KiB
LLVM
130 lines
6.7 KiB
LLVM
; RUN: llc < %s -mcpu=cortex-a8 -march=thumb
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; Test that this doesn't crash.
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; <rdar://problem/12183003>
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target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
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target triple = "thumbv7-apple-ios5.1.0"
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declare { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8(i8*, i32) nounwind readonly
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declare void @llvm.arm.neon.vst1.v16i8(i8*, <16 x i8>, i32) nounwind
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define void @findEdges(i8*) nounwind ssp {
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%2 = icmp sgt i32 undef, 0
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br i1 %2, label %5, label %3
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; <label>:3 ; preds = %5, %1
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%4 = phi i8* [ %0, %1 ], [ %19, %5 ]
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ret void
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; <label>:5 ; preds = %5, %1
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%6 = phi i8* [ %19, %5 ], [ %0, %1 ]
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%7 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8(i8* null, i32 1)
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%8 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %7, 0
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%9 = getelementptr inbounds i8* null, i32 3
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%10 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8(i8* %9, i32 1)
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%11 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %10, 2
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%12 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8(i8* %6, i32 1)
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%13 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %12, 0
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%14 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %12, 1
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%15 = getelementptr inbounds i8* %6, i32 3
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%16 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8(i8* %15, i32 1)
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%17 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %16, 1
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%18 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %16, 2
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%19 = getelementptr inbounds i8* %6, i32 48
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%20 = bitcast <16 x i8> %13 to <2 x i64>
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%21 = bitcast <16 x i8> %8 to <2 x i64>
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%22 = bitcast <16 x i8> %14 to <2 x i64>
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%23 = shufflevector <2 x i64> %22, <2 x i64> undef, <1 x i32> zeroinitializer
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%24 = bitcast <1 x i64> %23 to <8 x i8>
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%25 = zext <8 x i8> %24 to <8 x i16>
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%26 = sub <8 x i16> zeroinitializer, %25
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%27 = bitcast <16 x i8> %17 to <2 x i64>
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%28 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %26) nounwind
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%29 = mul <8 x i16> %28, %28
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%30 = add <8 x i16> zeroinitializer, %29
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%31 = tail call <8 x i16> @llvm.arm.neon.vmaxu.v8i16(<8 x i16> undef, <8 x i16> %30) nounwind
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%32 = bitcast <16 x i8> %11 to <2 x i64>
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%33 = shufflevector <2 x i64> %32, <2 x i64> undef, <1 x i32> zeroinitializer
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%34 = bitcast <1 x i64> %33 to <8 x i8>
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%35 = zext <8 x i8> %34 to <8 x i16>
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%36 = sub <8 x i16> %35, zeroinitializer
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%37 = bitcast <16 x i8> %18 to <2 x i64>
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%38 = shufflevector <2 x i64> %37, <2 x i64> undef, <1 x i32> zeroinitializer
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%39 = bitcast <1 x i64> %38 to <8 x i8>
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%40 = zext <8 x i8> %39 to <8 x i16>
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%41 = sub <8 x i16> zeroinitializer, %40
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%42 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %36) nounwind
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%43 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %41) nounwind
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%44 = mul <8 x i16> %42, %42
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%45 = mul <8 x i16> %43, %43
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%46 = add <8 x i16> %45, %44
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%47 = tail call <8 x i16> @llvm.arm.neon.vmaxu.v8i16(<8 x i16> %31, <8 x i16> %46) nounwind
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%48 = bitcast <8 x i16> %47 to <2 x i64>
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%49 = shufflevector <2 x i64> %48, <2 x i64> undef, <1 x i32> zeroinitializer
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%50 = bitcast <1 x i64> %49 to <4 x i16>
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%51 = tail call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> %50, <4 x i16> undef) nounwind
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%52 = tail call <4 x i16> @llvm.arm.neon.vqshiftnu.v4i16(<4 x i32> %51, <4 x i32> <i32 -6, i32 -6, i32 -6, i32 -6>)
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%53 = bitcast <4 x i16> %52 to <1 x i64>
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%54 = shufflevector <1 x i64> %53, <1 x i64> undef, <2 x i32> <i32 0, i32 1>
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%55 = bitcast <2 x i64> %54 to <8 x i16>
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%56 = tail call <8 x i8> @llvm.arm.neon.vshiftn.v8i8(<8 x i16> %55, <8 x i16> <i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8>)
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%57 = shufflevector <2 x i64> %20, <2 x i64> undef, <1 x i32> <i32 1>
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%58 = bitcast <1 x i64> %57 to <8 x i8>
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%59 = zext <8 x i8> %58 to <8 x i16>
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%60 = sub <8 x i16> zeroinitializer, %59
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%61 = shufflevector <2 x i64> %21, <2 x i64> undef, <1 x i32> <i32 1>
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%62 = bitcast <1 x i64> %61 to <8 x i8>
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%63 = zext <8 x i8> %62 to <8 x i16>
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%64 = sub <8 x i16> %63, zeroinitializer
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%65 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %60) nounwind
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%66 = mul <8 x i16> %65, %65
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%67 = add <8 x i16> zeroinitializer, %66
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%68 = shufflevector <2 x i64> %27, <2 x i64> undef, <1 x i32> <i32 1>
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%69 = bitcast <1 x i64> %68 to <8 x i8>
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%70 = zext <8 x i8> %69 to <8 x i16>
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%71 = sub <8 x i16> zeroinitializer, %70
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%72 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> undef) nounwind
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%73 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %71) nounwind
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%74 = mul <8 x i16> %72, %72
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%75 = mul <8 x i16> %73, %73
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%76 = add <8 x i16> %75, %74
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%77 = shufflevector <2 x i64> %32, <2 x i64> undef, <1 x i32> <i32 1>
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%78 = bitcast <1 x i64> %77 to <8 x i8>
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%79 = zext <8 x i8> %78 to <8 x i16>
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%80 = sub <8 x i16> %79, zeroinitializer
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%81 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %80) nounwind
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%82 = mul <8 x i16> %81, %81
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%83 = add <8 x i16> zeroinitializer, %82
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%84 = tail call <8 x i16> @llvm.arm.neon.vmaxu.v8i16(<8 x i16> %76, <8 x i16> %83) nounwind
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%85 = tail call <8 x i16> @llvm.arm.neon.vmaxu.v8i16(<8 x i16> %67, <8 x i16> %84) nounwind
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%86 = bitcast <8 x i16> %85 to <2 x i64>
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%87 = shufflevector <2 x i64> %86, <2 x i64> undef, <1 x i32> <i32 1>
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%88 = bitcast <1 x i64> %87 to <4 x i16>
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%89 = tail call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> %88, <4 x i16> undef) nounwind
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%90 = tail call <4 x i16> @llvm.arm.neon.vqrshiftnu.v4i16(<4 x i32> %89, <4 x i32> <i32 -6, i32 -6, i32 -6, i32 -6>)
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%91 = bitcast <4 x i16> %90 to <1 x i64>
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%92 = shufflevector <1 x i64> undef, <1 x i64> %91, <2 x i32> <i32 0, i32 1>
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%93 = bitcast <2 x i64> %92 to <8 x i16>
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%94 = tail call <8 x i8> @llvm.arm.neon.vshiftn.v8i8(<8 x i16> %93, <8 x i16> <i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8>)
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%95 = bitcast <8 x i8> %56 to <1 x i64>
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%96 = bitcast <8 x i8> %94 to <1 x i64>
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%97 = shufflevector <1 x i64> %95, <1 x i64> %96, <2 x i32> <i32 0, i32 1>
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%98 = bitcast <2 x i64> %97 to <16 x i8>
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tail call void @llvm.arm.neon.vst1.v16i8(i8* null, <16 x i8> %98, i32 1)
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%99 = icmp slt i32 undef, undef
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br i1 %99, label %5, label %3
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}
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declare <4 x i16> @llvm.arm.neon.vqshiftnu.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
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declare <8 x i8> @llvm.arm.neon.vshiftn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vqrshiftnu.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
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declare <8 x i16> @llvm.arm.neon.vmaxu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
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declare <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16>) nounwind readnone
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