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Differential revision: https://reviews.llvm.org/D72701 The patch adds a new option ABI for Hexagon. It primary deals with the way variable arguments are passed and is use in the Hexagon Linux Musl environment. If a callee function has a variable argument list, it must perform the following operations to set up its function prologue: 1. Determine the number of registers which could have been used for passing unnamed arguments. This can be calculated by counting the number of registers used for passing named arguments. For example, if the callee function is as follows: int foo(int a, ...){ ... } ... then register R0 is used to access the argument ' a '. The registers available for passing unnamed arguments are R1, R2, R3, R4, and R5. 2. Determine the number and size of the named arguments on the stack. 3. If the callee has named arguments on the stack, it should copy all of these arguments to a location below the current position on the stack, and the difference should be the size of the register-saved area plus padding (if any is necessary). The register-saved area constitutes all the registers that could have been used to pass unnamed arguments. If the number of registers forming the register-saved area is odd, it requires 4 bytes of padding; if the number is even, no padding is required. This is done to ensure an 8-byte alignment on the stack. For example, if the callee is as follows: int foo(int a, ...){ ... } ... then the named arguments should be copied to the following location: current_position - 5 (for R1-R5) * 4 (bytes) - 4 (bytes of padding) If the callee is as follows: int foo(int a, int b, ...){ ... } ... then the named arguments should be copied to the following location: current_position - 4 (for R2-R5) * 4 (bytes) - 0 (bytes of padding) 4. After any named arguments have been copied, copy all the registers that could have been used to pass unnamed arguments on the stack. If the number of registers is odd, leave 4 bytes of padding and then start copying them on the stack; if the number is even, no padding is required. This constitutes the register-saved area. If padding is required, ensure that the start location of padding is 8-byte aligned. If no padding is required, ensure that the start location of the on-stack copy of the first register which might have a variable argument is 8-byte aligned. 5. Decrement the stack pointer by the size of register saved area plus the padding. For example, if the callee is as follows: int foo(int a, ...){ ... } ; ... then the decrement value should be the following: 5 (for R1-R5) * 4 (bytes) + 4 (bytes of padding) = 24 bytes The decrement should be performed before the allocframe instruction. Increment the stack-pointer back by the same amount before returning from the function.
91 lines
3.3 KiB
C++
91 lines
3.3 KiB
C++
//=- HexagonMachineFunctionInfo.h - Hexagon machine function info -*- C++ -*-=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINEFUNCTIONINFO_H
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#define LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINEFUNCTIONINFO_H
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#include "llvm/CodeGen/MachineFunction.h"
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#include <map>
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namespace llvm {
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namespace Hexagon {
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const unsigned int StartPacket = 0x1;
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const unsigned int EndPacket = 0x2;
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} // end namespace Hexagon
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/// Hexagon target-specific information for each MachineFunction.
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class HexagonMachineFunctionInfo : public MachineFunctionInfo {
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// SRetReturnReg - Some subtargets require that sret lowering includes
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// returning the value of the returned struct in a register. This field
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// holds the virtual register into which the sret argument is passed.
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unsigned SRetReturnReg = 0;
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unsigned StackAlignBaseVReg = 0; // Aligned-stack base register (virtual)
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unsigned StackAlignBasePhysReg = 0; // (physical)
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int VarArgsFrameIndex;
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int RegSavedAreaStartFrameIndex;
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int FirstNamedArgFrameIndex;
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int LastNamedArgFrameIndex;
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bool HasClobberLR = false;
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bool HasEHReturn = false;
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std::map<const MachineInstr*, unsigned> PacketInfo;
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virtual void anchor();
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public:
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HexagonMachineFunctionInfo() = default;
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HexagonMachineFunctionInfo(MachineFunction &MF) {}
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unsigned getSRetReturnReg() const { return SRetReturnReg; }
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void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; }
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void setVarArgsFrameIndex(int v) { VarArgsFrameIndex = v; }
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int getVarArgsFrameIndex() { return VarArgsFrameIndex; }
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void setRegSavedAreaStartFrameIndex(int v) { RegSavedAreaStartFrameIndex = v;}
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int getRegSavedAreaStartFrameIndex() { return RegSavedAreaStartFrameIndex; }
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void setFirstNamedArgFrameIndex(int v) { FirstNamedArgFrameIndex = v; }
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int getFirstNamedArgFrameIndex() { return FirstNamedArgFrameIndex; }
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void setLastNamedArgFrameIndex(int v) { LastNamedArgFrameIndex = v; }
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int getLastNamedArgFrameIndex() { return LastNamedArgFrameIndex; }
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void setStartPacket(MachineInstr* MI) {
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PacketInfo[MI] |= Hexagon::StartPacket;
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}
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void setEndPacket(MachineInstr* MI) {
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PacketInfo[MI] |= Hexagon::EndPacket;
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}
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bool isStartPacket(const MachineInstr* MI) const {
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return (PacketInfo.count(MI) &&
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(PacketInfo.find(MI)->second & Hexagon::StartPacket));
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}
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bool isEndPacket(const MachineInstr* MI) const {
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return (PacketInfo.count(MI) &&
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(PacketInfo.find(MI)->second & Hexagon::EndPacket));
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}
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void setHasClobberLR(bool v) { HasClobberLR = v; }
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bool hasClobberLR() const { return HasClobberLR; }
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bool hasEHReturn() const { return HasEHReturn; };
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void setHasEHReturn(bool H = true) { HasEHReturn = H; };
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void setStackAlignBaseVReg(unsigned R) { StackAlignBaseVReg = R; }
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unsigned getStackAlignBaseVReg() const { return StackAlignBaseVReg; }
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void setStackAlignBasePhysReg(unsigned R) { StackAlignBasePhysReg = R; }
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unsigned getStackAlignBasePhysReg() const { return StackAlignBasePhysReg; }
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINEFUNCTIONINFO_H
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