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https://github.com/RPCS3/llvm-mirror.git
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60d312012b
Added relocation names: - R_AMDGPU_GOTPCREL32_LO - R_AMDGPU_GOTPCREL32_HI - R_AMDGPU_REL32_LO - R_AMDGPU_REL32_HI AMDGPU isa only supports 32-bit immediates. In order to access 64-bit address we need to generate 32-bit lo/hi relocations, and do the right math (separate patch). Currently we only generate one 32 bit relocation for lower bits for each access, losing higher bits. Hence we need relocations listed above. Differential Revision: https://reviews.llvm.org/D25546 llvm-svn: 284191
87 lines
2.6 KiB
YAML
87 lines
2.6 KiB
YAML
# RUN: yaml2obj %s > %t
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# RUN: llvm-readobj -r %t | FileCheck %s
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# CHECK: Relocations [
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# CHECK: Section (2) .rela.text {
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# CHECK: 0x0 R_AMDGPU_NONE - 0x0
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# CHECK: 0x2 R_AMDGPU_ABS32_LO - 0x0
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# CHECK: 0x4 R_AMDGPU_ABS32_HI - 0x0
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# CHECK: 0x6 R_AMDGPU_ABS64 - 0x0
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# CHECK: 0x8 R_AMDGPU_REL32 - 0x0
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# CHECK: 0x10 R_AMDGPU_REL64 - 0x0
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# CHECK: 0x12 R_AMDGPU_ABS32 - 0x0
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# CHECK: 0x14 R_AMDGPU_GOTPCREL - 0x0
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# CHECK: 0x16 R_AMDGPU_GOTPCREL32_LO - 0x0
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# CHECK: 0x18 R_AMDGPU_GOTPCREL32_HI - 0x0
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# CHECK: 0x20 R_AMDGPU_REL32_LO - 0x0
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# CHECK: 0x22 R_AMDGPU_REL32_HI - 0x0
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# CHECK: }
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# CHECK: ]
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!ELF
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FileHeader:
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Class: ELFCLASS64
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Data: ELFDATA2LSB
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Type: ET_REL
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Machine: EM_AMDGPU
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Sections:
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- Type: SHT_PROGBITS
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Name: .text
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Flags: [ SHF_ALLOC, SHF_EXECINSTR ]
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AddressAlign: 0x08
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Content: 0000000000000000
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- Type: SHT_RELA
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Name: .rela.text
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Link: .symtab
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Info: .text
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AddressAlign: 0x08
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Relocations:
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- Offset: 0x0
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Symbol: s0
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Type: R_AMDGPU_NONE
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- Offset: 0x2
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Symbol: s1
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Type: R_AMDGPU_ABS32_LO
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- Offset: 0x4
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Symbol: s2
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Type: R_AMDGPU_ABS32_HI
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- Offset: 0x6
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Symbol: s3
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Type: R_AMDGPU_ABS64
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- Offset: 0x8
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Symbol: s4
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Type: R_AMDGPU_REL32
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- Offset: 0x10
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Symbol: s5
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Type: R_AMDGPU_REL64
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- Offset: 0x12
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Symbol: s6
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Type: R_AMDGPU_ABS32
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- Offset: 0x14
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Symbol: s7
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Type: R_AMDGPU_GOTPCREL
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- Offset: 0x16
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Symbol: s8
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Type: R_AMDGPU_GOTPCREL32_LO
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- Offset: 0x18
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Symbol: s9
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Type: R_AMDGPU_GOTPCREL32_HI
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- Offset: 0x20
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Symbol: s10
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Type: R_AMDGPU_REL32_LO
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- Offset: 0x22
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Symbol: s11
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Type: R_AMDGPU_REL32_HI
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Symbols:
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Local:
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- Name: .text
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Type: STT_SECTION
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Section: .text
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Global:
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- Name: main
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Type: STT_FUNC
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Section: .text
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Size: 0x08
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