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44ebb7579c
This is based on the assumption that most simulated instructions don't define more than one or two registers. This is true for example on x86, where most instruction definitions don't declare more than one register write. The default code region size has been increased from 8 to 16. This is based on the assumption that, for small microbenchmarks, the typical code snippet size is often less than 16 instructions. mca::Instruction now uses bitfields to pack flags. No functional change intended.
78 lines
2.7 KiB
C++
78 lines
2.7 KiB
C++
//===--------------------- InstrBuilder.h -----------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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///
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/// A builder class for instructions that are statically analyzed by llvm-mca.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_MCA_INSTRBUILDER_H
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#define LLVM_MCA_INSTRBUILDER_H
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#include "llvm/MC/MCInstrAnalysis.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MCA/Instruction.h"
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#include "llvm/MCA/Support.h"
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#include "llvm/Support/Error.h"
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namespace llvm {
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namespace mca {
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/// A builder class that knows how to construct Instruction objects.
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///
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/// Every llvm-mca Instruction is described by an object of class InstrDesc.
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/// An InstrDesc describes which registers are read/written by the instruction,
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/// as well as the instruction latency and hardware resources consumed.
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///
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/// This class is used by the tool to construct Instructions and instruction
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/// descriptors (i.e. InstrDesc objects).
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/// Information from the machine scheduling model is used to identify processor
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/// resources that are consumed by an instruction.
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class InstrBuilder {
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const MCSubtargetInfo &STI;
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const MCInstrInfo &MCII;
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const MCRegisterInfo &MRI;
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const MCInstrAnalysis *MCIA;
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SmallVector<uint64_t, 8> ProcResourceMasks;
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DenseMap<unsigned short, std::unique_ptr<const InstrDesc>> Descriptors;
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DenseMap<const MCInst *, std::unique_ptr<const InstrDesc>> VariantDescriptors;
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bool FirstCallInst;
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bool FirstReturnInst;
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Expected<const InstrDesc &> createInstrDescImpl(const MCInst &MCI);
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Expected<const InstrDesc &> getOrCreateInstrDesc(const MCInst &MCI);
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InstrBuilder(const InstrBuilder &) = delete;
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InstrBuilder &operator=(const InstrBuilder &) = delete;
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void populateWrites(InstrDesc &ID, const MCInst &MCI, unsigned SchedClassID);
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void populateReads(InstrDesc &ID, const MCInst &MCI, unsigned SchedClassID);
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Error verifyInstrDesc(const InstrDesc &ID, const MCInst &MCI) const;
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public:
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InstrBuilder(const MCSubtargetInfo &STI, const MCInstrInfo &MCII,
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const MCRegisterInfo &RI, const MCInstrAnalysis *IA);
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void clear() {
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Descriptors.clear();
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VariantDescriptors.clear();
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FirstCallInst = true;
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FirstReturnInst = true;
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}
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Expected<std::unique_ptr<Instruction>> createInstruction(const MCInst &MCI);
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};
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} // namespace mca
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} // namespace llvm
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#endif // LLVM_MCA_INSTRBUILDER_H
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