Chen Zheng 921995afd5 Revert "[HardwareLoops] Change order of SCEV expression construction for InitLoopCount." ... This causes https://bugs.llvm.org/show_bug.cgi?id=51714 and is not a right patch according to comments in D91724 This reverts commit 42eaf4fe0adef3344adfd9fbccd49f325cb549ef. (cherry picked from commit 34badc409cc452575c538c4b6449546adc38f121)		2021-09-08 20:46:17 -07:00
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AArch64	[AArch64][sve] Prevent incorrect function call on fixed width vector	2021-09-08 06:09:19 -07:00
AMDGPU	AMDGPU/GlobalISel: Fix selecting G_SEXTLOAD/G_ZEXTLOAD pre-gfx9	2021-07-27 15:56:42 -04:00
ARC
ARM	[ARM][atomicrmw] Fix CMP_SWAP_32 expand assert	2021-08-18 12:14:24 -07:00
AVR
BPF	BPF: avoid NE/EQ loop exit condition	2021-08-06 12:45:53 -07:00
Generic
Hexagon	[Hexagon] Fix resetting dead registers in DBG_VALUE_LISTs	2021-07-27 18:36:28 -05:00
Inputs
Lanai
M68k
Mips
MIR
MSP430
NVPTX
PowerPC	Revert "[HardwareLoops] Change order of SCEV expression construction for InitLoopCount."	2021-09-08 20:46:17 -07:00
RISCV	[RISCV] Fix reporting of incorrect commutable operand indices	2021-09-03 15:48:26 -07:00
SPARC
SystemZ	[SystemZ][z/OS] Initial code to generate assembly files on z/OS	2021-07-27 11:29:15 -04:00
Thumb
Thumb2
VE
WebAssembly	[WebAssembly] Fix FastISel of condition in different block (PR51651)	2021-08-31 20:58:25 -07:00
WinCFGuard
WinEH
X86	[SelectionDAGBuilder] Bugfix in visitInlineAsm()	2021-09-08 14:03:50 -07:00
XCore