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154 lines
5.8 KiB
C++
154 lines
5.8 KiB
C++
//===-- NVPTXTargetTransformInfo.cpp - NVPTX specific TTI -----------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "NVPTXTargetTransformInfo.h"
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#include "NVPTXUtilities.h"
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#include "llvm/Analysis/LoopInfo.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/Analysis/ValueTracking.h"
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#include "llvm/CodeGen/BasicTTIImpl.h"
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#include "llvm/CodeGen/CostTable.h"
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#include "llvm/CodeGen/TargetLowering.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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#define DEBUG_TYPE "NVPTXtti"
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// Whether the given intrinsic reads threadIdx.x/y/z.
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static bool readsThreadIndex(const IntrinsicInst *II) {
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switch (II->getIntrinsicID()) {
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default: return false;
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case Intrinsic::nvvm_read_ptx_sreg_tid_x:
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case Intrinsic::nvvm_read_ptx_sreg_tid_y:
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case Intrinsic::nvvm_read_ptx_sreg_tid_z:
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return true;
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}
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}
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static bool readsLaneId(const IntrinsicInst *II) {
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return II->getIntrinsicID() == Intrinsic::nvvm_read_ptx_sreg_laneid;
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}
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// Whether the given intrinsic is an atomic instruction in PTX.
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static bool isNVVMAtomic(const IntrinsicInst *II) {
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switch (II->getIntrinsicID()) {
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default: return false;
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case Intrinsic::nvvm_atomic_load_add_f32:
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case Intrinsic::nvvm_atomic_load_inc_32:
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case Intrinsic::nvvm_atomic_load_dec_32:
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case Intrinsic::nvvm_atomic_add_gen_f_cta:
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case Intrinsic::nvvm_atomic_add_gen_f_sys:
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case Intrinsic::nvvm_atomic_add_gen_i_cta:
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case Intrinsic::nvvm_atomic_add_gen_i_sys:
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case Intrinsic::nvvm_atomic_and_gen_i_cta:
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case Intrinsic::nvvm_atomic_and_gen_i_sys:
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case Intrinsic::nvvm_atomic_cas_gen_i_cta:
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case Intrinsic::nvvm_atomic_cas_gen_i_sys:
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case Intrinsic::nvvm_atomic_dec_gen_i_cta:
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case Intrinsic::nvvm_atomic_dec_gen_i_sys:
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case Intrinsic::nvvm_atomic_inc_gen_i_cta:
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case Intrinsic::nvvm_atomic_inc_gen_i_sys:
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case Intrinsic::nvvm_atomic_max_gen_i_cta:
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case Intrinsic::nvvm_atomic_max_gen_i_sys:
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case Intrinsic::nvvm_atomic_min_gen_i_cta:
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case Intrinsic::nvvm_atomic_min_gen_i_sys:
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case Intrinsic::nvvm_atomic_or_gen_i_cta:
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case Intrinsic::nvvm_atomic_or_gen_i_sys:
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case Intrinsic::nvvm_atomic_exch_gen_i_cta:
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case Intrinsic::nvvm_atomic_exch_gen_i_sys:
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case Intrinsic::nvvm_atomic_xor_gen_i_cta:
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case Intrinsic::nvvm_atomic_xor_gen_i_sys:
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return true;
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}
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}
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bool NVPTXTTIImpl::isSourceOfDivergence(const Value *V) {
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// Without inter-procedural analysis, we conservatively assume that arguments
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// to __device__ functions are divergent.
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if (const Argument *Arg = dyn_cast<Argument>(V))
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return !isKernelFunction(*Arg->getParent());
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if (const Instruction *I = dyn_cast<Instruction>(V)) {
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// Without pointer analysis, we conservatively assume values loaded from
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// generic or local address space are divergent.
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if (const LoadInst *LI = dyn_cast<LoadInst>(I)) {
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unsigned AS = LI->getPointerAddressSpace();
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return AS == ADDRESS_SPACE_GENERIC || AS == ADDRESS_SPACE_LOCAL;
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}
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// Atomic instructions may cause divergence. Atomic instructions are
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// executed sequentially across all threads in a warp. Therefore, an earlier
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// executed thread may see different memory inputs than a later executed
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// thread. For example, suppose *a = 0 initially.
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//
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// atom.global.add.s32 d, [a], 1
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//
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// returns 0 for the first thread that enters the critical region, and 1 for
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// the second thread.
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if (I->isAtomic())
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return true;
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if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) {
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// Instructions that read threadIdx are obviously divergent.
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if (readsThreadIndex(II) || readsLaneId(II))
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return true;
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// Handle the NVPTX atomic instrinsics that cannot be represented as an
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// atomic IR instruction.
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if (isNVVMAtomic(II))
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return true;
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}
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// Conservatively consider the return value of function calls as divergent.
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// We could analyze callees with bodies more precisely using
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// inter-procedural analysis.
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if (isa<CallInst>(I))
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return true;
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}
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return false;
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}
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int NVPTXTTIImpl::getArithmeticInstrCost(
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unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info,
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TTI::OperandValueKind Opd2Info, TTI::OperandValueProperties Opd1PropInfo,
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TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args) {
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// Legalize the type.
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std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty);
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int ISD = TLI->InstructionOpcodeToISD(Opcode);
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switch (ISD) {
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default:
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return BaseT::getArithmeticInstrCost(Opcode, Ty, Opd1Info, Opd2Info,
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Opd1PropInfo, Opd2PropInfo);
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case ISD::ADD:
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case ISD::MUL:
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case ISD::XOR:
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case ISD::OR:
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case ISD::AND:
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// The machine code (SASS) simulates an i64 with two i32. Therefore, we
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// estimate that arithmetic operations on i64 are twice as expensive as
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// those on types that can fit into one machine register.
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if (LT.second.SimpleTy == MVT::i64)
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return 2 * LT.first;
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// Delegate other cases to the basic TTI.
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return BaseT::getArithmeticInstrCost(Opcode, Ty, Opd1Info, Opd2Info,
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Opd1PropInfo, Opd2PropInfo);
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}
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}
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void NVPTXTTIImpl::getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
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TTI::UnrollingPreferences &UP) {
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BaseT::getUnrollingPreferences(L, SE, UP);
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// Enable partial unrolling and runtime unrolling, but reduce the
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// threshold. This partially unrolls small loops which are often
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// unrolled by the PTX to SASS compiler and unrolling earlier can be
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// beneficial.
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UP.Partial = UP.Runtime = true;
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UP.PartialThreshold = UP.Threshold / 4;
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}
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