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111 lines
3.9 KiB
Plaintext
111 lines
3.9 KiB
Plaintext
Thu Jun 26 14:43:04 CDT 2003
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Information about BinInterface
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------------------------------
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Take in a set of instructions with some particular register
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allocation. It allows you to add, modify, or delete some instructions,
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in SSA form (kind of like LLVM's MachineInstrs.) Then re-allocate
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registers. It assumes that the transformations you are doing are safe.
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It does not update the mapping information or the LLVM representation
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for the modified trace (so it would not, for instance, support
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multiple optimization passes; passes have to be aware of and update
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manually the mapping information.)
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The way you use it is you take the original code and provide it to
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BinInterface; then you do optimizations to it, then you put it in the
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trace cache.
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The BinInterface tries to find live-outs for traces so that it can do
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register allocation on just the trace, and stitch the trace back into
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the original code. It has to preserve the live-ins and live-outs when
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it does its register allocation. (On exits from the trace we have
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epilogues that copy live-outs back into the right registers, but
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live-ins have to be in the right registers.)
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Limitations of BinInterface
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---------------------------
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It does copy insertions for PHIs, which it infers from the machine
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code. The mapping info inserted by LLC is not sufficient to determine
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the PHIs.
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It does not handle integer or floating-point condition codes and it
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does not handle floating-point register allocation.
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It is not aggressively able to use lots of registers.
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There is a problem with alloca: we cannot find our spill space for
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spilling registers, normally allocated on the stack, if the trace
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follows an alloca(). What might be an acceptable solution would be to
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disable trace generation on functions that have variable-sized
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alloca()s. Variable-sized allocas in the trace would also probably
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screw things up.
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Because of the FP and alloca limitations, the BinInterface is
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completely disabled right now.
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Demo
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----
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This is a demo of the Ball & Larus version that does NOT use 2-level
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profiling.
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1. Compile program with llvm-gcc.
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2. Run opt -lowerswitch -paths -emitfuncs on the bytecode.
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-lowerswitch change switch statements to branches
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-paths Ball & Larus path-profiling algorithm
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-emitfuncs emit the table of functions
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3. Run llc to generate SPARC assembly code for the result of step 2.
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4. Use g++ to link the (instrumented) assembly code.
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We use a script to do all this:
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------------------------------------------------------------------------------
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#!/bin/sh
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llvm-gcc $1.c -o $1
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opt -lowerswitch -paths -emitfuncs $1.bc > $1.run.bc
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llc -f $1.run.bc
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LIBS=$HOME/llvm_sparc/lib/Debug
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GXX=/usr/dcs/software/evaluation/bin/g++
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$GXX -g -L $LIBS $1.run.s -o $1.run.llc \
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$LIBS/tracecache.o \
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$LIBS/mapinfo.o \
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$LIBS/trigger.o \
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$LIBS/profpaths.o \
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$LIBS/bininterface.o \
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$LIBS/support.o \
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$LIBS/vmcore.o \
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$LIBS/transformutils.o \
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$LIBS/bcreader.o \
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-lscalaropts -lscalaropts -lanalysis \
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-lmalloc -lcpc -lm -ldl
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------------------------------------------------------------------------------
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5. Run the resulting binary. You will see output from BinInterface
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(described below) intermixed with the output from the program.
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Output from BinInterface
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------------------------
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BinInterface's debugging code prints out the following stuff in order:
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1. Initial code provided to BinInterface with original register
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allocation.
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2. Section 0 is the trace prolog, consisting mainly of live-ins and
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register saves which will be restored in epilogs.
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3. Section 1 is the trace itself, in SSA form used by BinInterface,
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along with the PHIs that are inserted.
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PHIs are followed by the copies that implement them.
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Each branch (i.e., out of the trace) is annotated with the
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section number that represents the epilog it branches to.
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4. All the other sections starting with Section 2 are trace epilogs.
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Every branch from the trace has to go to some epilog.
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5. After the last section is the register allocation output.
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